Re: [PATCH v2 1/2] dt-bindings: phy: ti,phy-usb3: Add aspcie reference clock setting

On Thu, Aug 06, 2026 at 11:11:11AM +0200, David Oberhollenzer wrote:
> The PHY control logic in the OMAP PCIe PHY subsystem has a
> configurable reference clock selection. It can either use
> the ljcb_clkp/ljcb_clkn pin as inputs, recovering the clock
> from the bus (RX mode), or generate the reference clock
> internally, driving the bus pins as outputs (TX mode).
> 
> The setting is exposed through a register in a system controller.
> A device tree property is added to specify the syscon node,
> register offset and mode value.
> 
> Signed-off-by: David Oberhollenzer <[email protected]>
> ---
>  .../devicetree/bindings/phy/ti,phy-usb3.yaml  | 39 +++++++++++++++++++
>  1 file changed, 39 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> index 84f538aa587c..11787b042345 100644
> --- a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> @@ -52,6 +52,20 @@ properties:
>        enum: [wkupclk, sysclk, refclk, dpll_ref,
>               dpll_ref_m2, phy-div, div-clk]
>  
> +  ti,syscon-acspcie-tx-rx:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    description: |

Don't need '|' unless there is formatting to preserve.

> +      Syscon register and setting to configure the clock buffer to run
> +      in RX mode (clock pins are inputs, the clock is recovered from
> +      the bus), or in TX mode (pins are outputs, internal reference
> +      clock drives the bus).

Wrap lines at 80 chars.

> +    maxItems: 1
> +    items:
> +      items:
> +        - description: Phandle to the system control module
> +        - description: Register offset of CTRL_CORE_SMA_SW_6
> +        - description: Setting for PCIE_TX_RX_CONTROL
> +
>    syscon-phy-power:
>      $ref: /schemas/types.yaml#/definitions/phandle-array
>      maxItems: 1
> @@ -94,6 +107,17 @@ allOf:
>      else:
>        properties:
>          syscon-pllreset: false
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: ti,phy-pipe3-pcie
> +    then:
> +      properties:
> +        ti,syscon-acspcie-tx-rx: true

This has no effect. Invert the if and move the else here.

> +    else:
> +      properties:
> +        ti,syscon-acspcie-tx-rx: false
>  
>  required:
>    - reg
> @@ -135,4 +159,19 @@ examples:
>          syscon-pllreset = <&scm_conf 0x3fc>;
>          #phy-cells = <0>;
>      };
> +
> +  - |
> +    /* TI PIPE3 PCIE PHY */
> +    pcie-phy@4a0a4000 {
> +        compatible = "ti,phy-pipe3-pcie";
> +        reg = <0x4a0a4000 0x80>,  /* phy_rx */
> +              <0x4a0a4400 0x64>;  /* phy_tx */
> +        reg-names = "phy_rx", "phy_tx";
> +        clocks = <&dpll_pcie_ref_ck>, <&dpll_pcie_ref_m2ldo_ck>;
> +        clock-names = "dpll_ref", "dpll_ref_m2";
> +        #phy-cells = <0>;
> +        syscon-phy-power = <&scm_conf_pcie 0x1c>;
> +        syscon-pcs = <&scm_conf_pcie 0x10>;
> +        ti,syscon-acspcie-tx-rx = <&scm_conf1 0x10 0x2>;
> +    };
>  ...
> -- 
> 2.55.0
> 

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