[PATCH v2 03/14] arm64: dts: qcom: ipq5018: Add USB Super-Speed PHY node
George Moussalem via B4 Relay <[email protected]>
| Newsgroups | org.infradead.lists.linux-phy,org.kernel.feeds.b4-sent,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-usb |
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| Message-ID | <[email protected]> |
From: George Moussalem <[email protected]> Add USB Super-Speed UNIPHY node and populate the USB DT clock on the GCC node for the GCC to gate the PIPE clock supplied by the USB3 PHY. Signed-off-by: George Moussalem <[email protected]> --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index 4fc627b47fe7..d259a841ad17 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -179,6 +179,23 @@ usbphy0: phy@5b000 { status = "disabled"; }; + usbphy1: phy@5d000 { + compatible = "qcom,ipq5018-uniphy-usb-ss-phy"; + reg = <0x0005d000 0x800>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + + resets = <&gcc GCC_USB0_PHY_BCR>; + + #clock-cells = <0>; + #phy-cells = <0>; + + qcom,phy-usb-mux-sel = <&tcsr 0x10540>; + + status = "disabled"; + }; + pcie1_phy: phy@7e000 { compatible = "qcom,ipq5018-uniphy-pcie-phy"; reg = <0x0007e000 0x800>; @@ -436,7 +453,7 @@ gcc: clock-controller@1800000 { <&sleep_clk>, <&pcie0_phy>, <&pcie1_phy>, - <0>, + <&usbphy1>, <&gephy_rx_clk>, <&gephy_tx_clk>, <0>, -- 2.53.0 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy