Re: [PATCH v2] phy: cadence: Sierra: Do not modify register when getting parent clock
Manivannan Sadhasivam <[email protected]>
| Newsgroups | org.infradead.lists.linux-phy,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <mbx5knxgp66lhtrbd5p7fwfngeqf6rfi6kcyifzhtbk4t4f3ou@cpdu5j7wvkfc> |
On Fri, Mar 06, 2026 at 11:23:58AM +0100, Gregory CLEMENT wrote:
> The get_parent() callback for the PLL_CMNLC1 clock was incorrectly
> writing to the register while determining the parent clock index. This
> unintended register access forces the PHY back into training mode. If
> the PHY is already configured, this unexpected change prevents it from
> exiting training mode.
>
> Remove the register write operation to ensure the PHY remains stable
> during the get_parent() callback.
>
> Fixes: da08aab940092 ("phy: cadence: Sierra: Fix to get correct parent for mux clocks")
> Signed-off-by: Gregory CLEMENT <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
- Mani
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