Re: [PATCH] riscv: cmpxchg: Use .option arch for Zacas and Zabha
Jesse Taube <[email protected]>
| Newsgroups | org.infradead.lists.linux-riscv,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <CADRr4bfXgfGu2EezHptWa04ZiH1JXcXWh2Qz+6nQMH98w00Jbg@mail.gmail.com> |
On Fri, Jul 17, 2026 at 11:49 AM Vivian Wang <[email protected]> wrote: > > Instead of adding these to -march globally, use .option arch to use > instructions from these extensions only in code paths where we know they > are available, like how it is done for most other extensions. > TOOLCHAIN_HAS_{ZACAS,ZABHA} already depend on AS_HAS_OPTION_ARCH, so > this is not a functionality regression even on older assemblers. > > Although the compiler is unlikely to generate atomics on its own accord, > this aligns handling of Zacas and Zabha with most other extensions and > improves consistency on how assembly code requiring extra extensions is > written in kernel code. > > This is analogous to the use of __LSE_PREAMBLE or .arch_extension lse in > arm64 code. > > Signed-off-by: Vivian Wang <[email protected]> Reviewed-by: Jesse Taube <[email protected]> > --- > arch/riscv/Makefile | 6 ------ > arch/riscv/include/asm/cmpxchg.h | 14 +++++++++++++- > 2 files changed, 13 insertions(+), 7 deletions(-) > > diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile > index ce0cc737f870..4d74b141122c 100644 > --- a/arch/riscv/Makefile > +++ b/arch/riscv/Makefile > @@ -75,12 +75,6 @@ else > riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei > endif > > -# Check if the toolchain supports Zacas > -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas > - > -# Check if the toolchain supports Zabha > -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha > - > KBUILD_BASE_ISA = -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/') > export KBUILD_BASE_ISA > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > index 8712cf9c69dc..662e160b0522 100644 > --- a/arch/riscv/include/asm/cmpxchg.h > +++ b/arch/riscv/include/asm/cmpxchg.h > @@ -23,7 +23,10 @@ > riscv_has_extension_unlikely(RISCV_ISA_EXT_ZABHA)) { \ > __asm__ __volatile__ ( \ > prepend \ > + " .option push\n" \ > + " .option arch, +zabha\n" \ > " amoswap" swap_sfx " %0, %z2, %1\n" \ > + " .option pop\n" \ > swap_append \ > : "=&r" (r), "+A" (*(p)) \ > : "rJ" (n) \ > @@ -141,7 +144,10 @@ > \ > __asm__ __volatile__ ( \ > cas_prepend \ > + " .option push\n" \ > + " .option arch, +zacas, +zabha\n" \ > " amocas" cas_sfx " %0, %z2, %1\n" \ > + " .option pop\n" \ > cas_append \ > : "+&r" (r), "+A" (*(p)) \ > : "rJ" (n) \ > @@ -188,7 +194,10 @@ > \ > __asm__ __volatile__ ( \ > cas_prepend \ > + " .option push\n" \ > + " .option arch, +zacas\n" \ > " amocas" cas_sfx " %0, %z2, %1\n" \ > + " .option pop\n" \ > cas_append \ > : "+&r" (r), "+A" (*(p)) \ > : "rJ" (n) \ > @@ -340,7 +349,10 @@ union __u128_halves { > register unsigned long t4 asm ("t4") = __ho.high; \ > \ > __asm__ __volatile__ ( \ > - " amocas.q" cas_sfx " %0, %z3, %2" \ > + " .option push\n" \ > + " .option arch, +zacas\n" \ > + " amocas.q" cas_sfx " %0, %z3, %2\n" \ > + " .option pop\n" \ > : "+&r" (t3), "+&r" (t4), "+A" (*(p)) \ > : "rJ" (t1), "rJ" (t2) \ > : "memory"); \ > > --- > base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482 > change-id: 20260717-riscv-no-zacas-zabha-in-march-28e278a993a2 > > Best regards, > -- > Vivian Wang <[email protected]> > > > _______________________________________________ > linux-riscv mailing list > [email protected] > http://lists.infradead.org/mailman/listinfo/linux-riscv > _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv