Re: [PATCH 1/2] riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITX

Yixun Lan <[email protected]> Sat, 25 Jul 2026 01:10:30 +0000

Newsgroups	org.infradead.lists.linux-riscv,dev.linux.lists.spacemit,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel
Message-ID	<[email protected]>

Hi Inochi,

On 09:01 Sat 25 Jul     , Inochi Amaoto wrote:
> On Fri, Jul 10, 2026 at 10:38:04PM +0000, Yixun Lan wrote:
> > Hi Inochi,
> > 
> > On 14:33 Fri 10 Jul     , Inochi Amaoto wrote:
> > > RTL8211F require at least 50ms deassert to guarantee the register
> > > access, 10ms is only enough for the PHY reset.
> > > 
> > IMO, it's kind of too trivial to split into two separate patches,
> > while duplicating the commit message
> > 
> 
> For backport, I suggest keeping two patches, so it can be backported
> in a more clear way
> 
Ok, fine by me, I will queue the patches for v7.3

-- 
Yixun Lan (dlan)

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