[PATCH v5 2/3] riscv: dts: sophgo: cv180x: Add PWR_GPIO controller
Chen-Yu Yeh <[email protected]>
| Newsgroups | org.infradead.lists.linux-riscv,dev.linux.lists.sophgo,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
The CV180x/CV181x family has an additional DesignWare APB GPIO controller (PWR_GPIO) located in the always-on power domain at 0x5021000. Add the node so that boards can reference GPIOs in this bank, such as status LEDs. Signed-off-by: Chen-Yu Yeh <[email protected]> --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 06b0ce5a2db7..8bf67ee4eca5 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -448,6 +448,24 @@ usb: usb@4340000 { status = "disabled"; }; + gpio4: gpio@5021000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x5021000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porte: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <SOC_PERIPHERAL_IRQ(54) IRQ_TYPE_LEVEL_HIGH>; + }; + }; + rtc@5025000 { compatible = "sophgo,cv1800b-rtc", "syscon"; reg = <0x5025000 0x2000>; -- 2.43.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv