[PATCH v5 11/21] dt-bindings: pinctrl: Add starfive,jhb100-per0-pinctrl
Changhuang Liang <[email protected]>
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Add pinctrl bindings for StarFive JHB100 SoC Peripheral-0(per0) pinctrl controller. Signed-off-by: Changhuang Liang <[email protected]> --- .../pinctrl/starfive,jhb100-per0-pinctrl.yaml | 180 ++++++++++++++++++ .../pinctrl/starfive,jhb100-pinctrl.h | 62 ++++++ 2 files changed, 242 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml new file mode 100644 index 000000000000..596b284769a1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-per0-pinctrl.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-per0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-0 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "per0" pinctrl domain. + + The "per0" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the Peripheral-0 Pin Controller, there are 60 multi-function GPIO_PADs. + Each of them can be multiplexed to several hardware blocks through function + selection. Each iopad has a maximum of up to 3 functions - 0, 1, and 2. + Function 0 is the default function which is generally the GPIO function. + Function 1 and 2 are the alternate function or signal of an iopad. The + function 1 and function 2 are other optional functions or peripheral + signals that can be routed to an iopad. The function selection can be carried + out by writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source and drive type (open-drain or push-pull). + +maintainers: + - Changhuang Liang <[email protected]> + +properties: + compatible: + items: + - const: starfive,jhb100-per0-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + + gpio-controller: true + + '#gpio-cells': + const: 3 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + drive-open-drain, drive-push-pull, power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ gmac_mdio, gpio, i2c, i3c, smbalert, wdt ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + oneOf: + - type: boolean + - enum: [ 600, 900, 1200, 2000 ] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + drive-open-drain: true + + drive-push-pull: true + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-ns: + minimum: 0 + maximum: 10485680 + description: + Debounce time in nanoseconds. The hardware counts in 80 ns + stages with a 17-bit counter, so the maximum is 10485680 ns. + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 1800, 3300 ] + description: I/O voltage in millivolt. + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow + 1: fast + +required: + - compatible + - reg + - resets + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_per0: pinctrl@11a0a000 { + compatible = "starfive,jhb100-per0-pinctrl"; + reg = <0x0 0x11a0a000 0x0 0x1000>; + resets = <&per0crg 0>; + interrupts = <60>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_per0 0 0 0 32>, + <&pinctrl_per0 1 0 32 28>; + }; + }; diff --git a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h index e701c30913ce..e0ad453d6884 100644 --- a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h @@ -77,4 +77,66 @@ #define PADNUM_SYS2_GPIO_A59 35 #define PADNUM_SYS2_GPIO_A60 36 +/* per0 pad numbers */ +#define PADNUM_PER0_GPIO_B0 0 +#define PADNUM_PER0_GPIO_B1 1 +#define PADNUM_PER0_GPIO_B2 2 +#define PADNUM_PER0_GPIO_B3 3 +#define PADNUM_PER0_GPIO_B4 4 +#define PADNUM_PER0_GPIO_B5 5 +#define PADNUM_PER0_GPIO_B6 6 +#define PADNUM_PER0_GPIO_B7 7 +#define PADNUM_PER0_GPIO_B8 8 +#define PADNUM_PER0_GPIO_B9 9 +#define PADNUM_PER0_GPIO_B10 10 +#define PADNUM_PER0_GPIO_B11 11 +#define PADNUM_PER0_GPIO_B12 12 +#define PADNUM_PER0_GPIO_B13 13 +#define PADNUM_PER0_GPIO_B14 14 +#define PADNUM_PER0_GPIO_B15 15 +#define PADNUM_PER0_GPIO_B16 16 +#define PADNUM_PER0_GPIO_B17 17 +#define PADNUM_PER0_GPIO_B18 18 +#define PADNUM_PER0_GPIO_B19 19 +#define PADNUM_PER0_GPIO_B20 20 +#define PADNUM_PER0_GPIO_B21 21 +#define PADNUM_PER0_GPIO_B22 22 +#define PADNUM_PER0_GPIO_B23 23 +#define PADNUM_PER0_GPIO_B24 24 +#define PADNUM_PER0_GPIO_B25 25 +#define PADNUM_PER0_GPIO_B26 26 +#define PADNUM_PER0_GPIO_B27 27 +#define PADNUM_PER0_GPIO_B28 28 +#define PADNUM_PER0_GPIO_B29 29 +#define PADNUM_PER0_GPIO_B30 30 +#define PADNUM_PER0_GPIO_B31 31 +#define PADNUM_PER0_GPIO_B32 32 +#define PADNUM_PER0_GPIO_B33 33 +#define PADNUM_PER0_GPIO_B34 34 +#define PADNUM_PER0_GPIO_B35 35 +#define PADNUM_PER0_GPIO_B36 36 +#define PADNUM_PER0_GPIO_B37 37 +#define PADNUM_PER0_GPIO_B38 38 +#define PADNUM_PER0_GPIO_B39 39 +#define PADNUM_PER0_GPIO_B40 40 +#define PADNUM_PER0_GPIO_B41 41 +#define PADNUM_PER0_GPIO_B42 42 +#define PADNUM_PER0_GPIO_B43 43 +#define PADNUM_PER0_GPIO_B44 44 +#define PADNUM_PER0_GPIO_B45 45 +#define PADNUM_PER0_GPIO_B46 46 +#define PADNUM_PER0_GPIO_B47 47 +#define PADNUM_PER0_GPIO_B48 48 +#define PADNUM_PER0_GPIO_B49 49 +#define PADNUM_PER0_GPIO_B50 50 +#define PADNUM_PER0_GPIO_B51 51 +#define PADNUM_PER0_GPIO_B52 52 +#define PADNUM_PER0_GPIO_B53 53 +#define PADNUM_PER0_GPIO_B54 54 +#define PADNUM_PER0_GPIO_B55 55 +#define PADNUM_PER0_GPIO_B56 56 +#define PADNUM_PER0_GPIO_B57 57 +#define PADNUM_PER0_GPIO_B58 58 +#define PADNUM_PER0_GPIO_B59 59 + #endif -- 2.25.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv