Re: [PATCH v4 2/8] clk: starfive: Add system-0 domain PLL clock driver
Changhuang Liang <[email protected]>
| Newsgroups | org.infradead.lists.linux-riscv,org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
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| Message-ID | <ZQ4PR01MB1202021D10801575B515F9A6F2DD2@ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn> |
Hi, Conor > On Sat, Aug 08, 2026 at 06:50:48PM -0700, Changhuang Liang wrote: > > Add system-0 domain PLL clock driver for StarFive JHB100 SoC. > > > > Signed-off-by: Changhuang Liang <[email protected]> > > Could you please get either Hal or someone like Xingyu Wu to review the > clock driver changes? > Okay, I will ask them to help with the review. Best Regards, Changhuang _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv