[PATCH v4 4/7] riscv: dts: eswin: add hsp bus node
Pinkesh Vaghela <[email protected]>
| Newsgroups | org.infradead.lists.linux-riscv,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-i2c,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Add an HSP bus node to manage the HSP CFG clock used by HSP peripherals. This clock is required for accessing both the HSP CSR registers and the register spaces of HSP peripheral devices. Signed-off-by: Pinkesh Vaghela <[email protected]> --- arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index b16e3e28632c..771a88645d83 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -252,6 +252,19 @@ plic: interrupt-controller@c000000 { #interrupt-cells = <1>; }; + hsp: bus@50400000 { + compatible = "simple-pm-bus"; + ranges = <0x0 0x50400000 0x0 0x50400000 0x0 0xa0000>; + clocks = <&clk EIC7700_CLK_GATE_HSP_CFG_CLK>; + #address-cells = <2>; + #size-cells = <2>; + + syscon: syscon@50440000 { + compatible = "eswin,eic7700-syscfg", "syscon"; + reg = <0x0 0x50440000 0x0 0x2000>; + }; + }; + uart0: serial@50900000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x50900000 0x0 0x10000>; -- 2.34.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv