Re: [PATCH bpf-next 1/2] bpf, riscv: Add support for signed arena loads

>     bpf, riscv: Add support for signed arena loads
>
>     Signed loads from arena memory are currently rejected on riscv64, as
>     bpf_jit_supports_insn() refuses BPF_MEMSX loads when in_arena is set,
>     while x86 and arm64 gained support for them in v6.18. Compilers such
>     as GCC-14 are free to generate signed loads into arena memory, which
>     breaks loading of otherwise valid BPF programs on riscv64.
>
>     Implement BPF_PROBE_MEM32SX support in the RV64 JIT by reusing the
>     existing arena handling: the arena base (RV_REG_ARENA) is added to
>     the source register and the load is emitted with sign extension
>     (lb/lh/lw). Add BPF_PROBE_MEM32SX to the add_exception_handler()
>     mode gate so that faulting loads get an exception table entry which
>     clears the destination register and resumes execution.
>
>     Verified by running the arena LDSX selftests (arena_ldsx_disasm,
>     arena_ldsx_exception, arena_ldsx_s8/s16/s32) on riscv64 QEMU, all
>     passing.
>
>     Signed-off-by: Chen Pei <[email protected]>

This looks like a bug fix for incomplete arena support added by commit
fb7cefabae81. Should this include:

  Fixes: fb7cefabae81 ("riscv, bpf: Add support arena atomics for RV64")


---
AI reviewed your patch. Please fix the bug or email reply why it's not a bug.
See: https://github.com/kernel-patches/vmtest/blob/master/ci/claude/README.md

CI run summary: https://github.com/kernel-patches/bpf/actions/runs/32007452800

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