[PATCH v2 0/2] perf: RISC-V: fix SBI PMU masks for RV32
Xixin Liu <[email protected]>
| Newsgroups | org.infradead.lists.linux-riscv,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-kernel,org.kernel.vger.linux-perf-users |
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| Message-ID | <[email protected]> |
Hi, Thanks for the review, Paul. v2 for 1/2: add Fixes and Assisted-by. Overflow masks are u64. On RV32 an unsigned-long bit at index 32 is 0, and BIT_ULL at index 32 is 0x100000000. v2 for 2/2: same as v1, but do not pass only the first bitmap word into CFG_MATCH. Walk each word like the stop-all path, with the counter base set to i times BITS_PER_LONG. Share one helper for the 32-bit argument split. Also add Fixes and Assisted-by. Tested on qemu-system-riscv32 with CONFIG_ARCH_RV32I=y: 34 counters, second word 0x7, CFG_MATCH retried at base 32 when the first word fails. qemu-system-riscv64 still uses one word. A legacy-only RV32 kernel sets cycle and instret bits and opens a cycles event. Overflow IRQ was not taken on this QEMU virt guest, because sscof was not available to Linux. Thanks, Xixin Liu --- Xixin Liu (2): perf: RISC-V: use BIT_ULL for u64 overflow masks perf: RISC-V: store available counter mask as bitmap drivers/perf/riscv_pmu_legacy.c | 5 ++- drivers/perf/riscv_pmu_sbi.c | 88 ++++++++++++++++++++++++++++------------ include/linux/perf/riscv_pmu.h | 2 +- 3 files changed, 66 insertions(+), 29 deletions(-) -- 2.43.0 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv