Re: [PATCH] riscv: Add support for early boot errata application on MIPS chips
Aleksa Paunovic <[email protected]>
| Newsgroups | org.infradead.lists.linux-riscv,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Hi Paul, On 8/21/26 03:53, Paul Walmsley wrote: > On Mon, 10 Aug 2026, Aleksa Paunovic via B4 Relay wrote: > >> From: Aleksa Paunovic <[email protected]> >> >> MIPS errata implementation previously skipped early boot application >> entirely. Although the only currently existing MIPS erratum does not >> require this, amending this now should make any future addition easier to >> implement. >> >> This commit was based on the existing T-Head implementation. >> >> Suggested-by: Jesse Taube <[email protected]> >> Link: https://lore.kernel.org/linux-riscv/CADRr4bcbD57hmR0XGgo8BjgNp4shEADOondZEtwscCJ9-nxXRQ@mail.gmail.com/ >> Signed-off-by: Aleksa Paunovic <[email protected]> >> --- >> The patch was motivated by Jesse's suggestion to implement [2] as an early boot erratum. >> However, since it's in conflict with [1] as well, I decided against sending this one and the ZALRSC patch as a series, >> opting for rebasing [1] and [2] once it's clear we should move forward with this approach. >> >> I tested this on an eight-hart QEMU config. The testing was done by rebasing [1] and [2] onto the patch >> and running most of the same tests used to verify those patches. This includes: coremark testing, futex kselftests >> and GDB to check errata application. The same tests were run on the Boston board, configured with a single P8700 core. >> >> Links: >> [1] https://lore.kernel.org/linux-riscv/[email protected]/ >> [2] https://lore.kernel.org/linux-riscv/[email protected]/ > Thanks, queued for v7.4. Thanks a lot! Best regards, Aleksa _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv