Re: [PATCH v4 02/21] iommufd: Add iommufd_sw_map_msi()

On Fri, Aug 21, 2026 at 04:23:22PM +0200, Andrew Jones wrote:
> > But RISC-V IOMMU is also not involved in interrupt translation. Beyond
> > it could remap the PAs which represent the CPUs, but you are not using
> > it that way since it is statically setup.
> > 
> > So I'm not sure why the iommu gets an IR? Isn't it the same as ARM
> > where the IMSIC itself just has a wack of PAs it needs to access so it
> > calls iommu_dma_prepare_msi() to do it?
> 
> Right, this series is only remapping IMSIC PAs, not using the IOMMU MSI
> table. The MSI table must be disabled when second-stage translation is
> Bare, so it cannot be used for the host mappings here. It will be needed
> for guest interrupt files (the irqbypass series I'm also working on),
> where this IR irqdomain can then intercept irq_set_vcpu_affinity().
> Also, keeping the MSI setup in this IR irqdomain avoids putting IOMMU
> mapping knowledge in the IMSIC driver.

It's ok for the IMSIC driver to call iommu_dma_prepare_msi(), that's
the architecutre of this at least.

Until you get to adding something more complicated, eg irqbypass, I'd
suggest keeping this series simple.

I guess I would wonder why the IOMMU needs to be involved in changing
the mapping down the road, why not just reprogram the MSI-X address?

Jason

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