[RFC PATCH v2] arm64: dts: rockchip: H28K: release RTL8211F reset before MDIO probing

arm64: dts: rockchip: H28K: release RTL8211F reset before MDIO probing

On the HINLINK H28K (RK3528), the RTL8211F reset line (gpio4 RK_PC2,
pin 146) is left unconfigured at power-on and reads low, holding the
PHY in reset. The PHY node's reset-gpios are only acted upon after the
PHY has been found on MDIO (fwnode_mdiobus_register_phy() reads the
PHY ID before it requests and toggles the reset GPIO), so the first
probe deadlocks and eth0 never gets a link:

    mdio_bus stmmac-0: MDIO device at address 1 is missing.
    rk_gmac-dwmac ffbe0000.ethernet eth0: cannot attach to PHY
    (error: -ENODEV)

Move the reset to the MDIO bus level: mdiobus_register() asserts and
releases the bus reset-gpios before scanning the bus, so the PHY is
out of reset when its ID is read. The PHY node no longer declares
reset-gpios for the same GPIO (a second consumer would be rejected
with -EBUSY).

Fixes: 145d4af4b204 ("arm64: dts: rockchip: Add HINLINK H28K")
Signed-off-by: Zhyi <[email protected]>
Assisted-by: Codex:gpt-5
---
Changes in v2:
- The root-cause analysis and this fix were developed with the
  assistance of an AI coding assistant (Codex, GPT-5). The resulting
  DTS change is minimal and the hardware validation was done by a
  human on a stock HINLINK H28K board.
- This v2 supersedes the accidental duplicate of my v1 RFC sent from
  my Outlook address (Message-ID:
  SJ2PR04MB851017E50140354C2F5B3FF3B5D52@SJ2PR04MB8510.namprd04.prod.outlook.com);
  apologies for the duplicate.
- Use the standard MDIO bus reset properties (mdio.yaml reset-gpios,
  reset-delay-us, reset-post-delay-us) instead of the deprecated
  snps,reset-gpios on the MAC node, as suggested by Andrew Lunn.
- The PHY ID is not hardcoded, so boards populated with either the
  RTL8211F or the YT8531 work unchanged (as noted by Chukun Pan).
- Thanks to Andrew Lunn and Chukun Pan for the review feedback.
- Validated on the stock HINLINK H28K board with Linux 7.1.5:
  eth0 shows "PHY [stmmac-0:01] driver [RTL8211F Gigabit Ethernet]"
  and phy_id 0x001cc916; both eth0 (GMAC) and eth1 (PCIe RTL8111H)
  work.
- The U-Boot side (generic RK3528 DT does not configure the reset
  line) is out of scope for this DTS fix and may be addressed
  separately.
diff --git a/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts
index 0ec50e9..7ba3fa4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts
@@ -200,14 +200,14 @@
 };
 
 &mdio1 {
+	reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+	reset-delay-us = <20000>;
+	reset-post-delay-us = <100000>;
 	rgmii_phy: ethernet-phy@1 {
 		compatible = "ethernet-phy-ieee802.3-c22";
 		reg = <0x1>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&gmac1_rstn_l>;
-		reset-assert-us = <20000>;
-		reset-deassert-us = <100000>;
-		reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
 	};
 };
 


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