Re: [PATCH] platform: generic: mips eyeq7h: fix boot with JTAG

On Thu, Jun 18, 2026 at 4:07 PM Vladimir Kondratiev
<[email protected]> wrote:
>
> When JTAG is connected, internal logic leads to the bit
> MIPS_CTL0_DBG_RST_DASRT (for the debug unit) stay high and this
> prevents normal cluster power-up.
>
> Force proper power-on reset value prior to power-up sequence.
> Hold this value for about 10 usec
>
> Signed-off-by: Vladimir Kondratiev <[email protected]>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  platform/generic/mips/eyeq7h.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/platform/generic/mips/eyeq7h.c b/platform/generic/mips/eyeq7h.c
> index 242cbb3ce327..30af096c14f4 100644
> --- a/platform/generic/mips/eyeq7h.c
> +++ b/platform/generic/mips/eyeq7h.c
> @@ -73,7 +73,13 @@ static void eyeq7h_powerup_olb(u32 hartid)
>         /* Get the MIPS_CM_CTL0 address */
>         cmd = (volatile void *)(MIPS_OLB_ADDR[cl] + MIPS_CM_CTL0);
>
> -       temp = readl(cmd);
> +       /* set reset value. Value may be wrong after JTAG debug session */
> +       temp = MIPS_CTL0_CACHE_HW_INIT_INHIBIT |
> +              INSERT_FIELD(0, MIPS_CTL0_DBU_COLD_PWR_UP, 2) |
> +              MIPS_CTL0_DBU_PWR_UP | MIPS_CTL0_CM_PWR_UP;
> +       writel(temp, cmd);
> +       wmb();
> +       sbi_timer_udelay(10);
>         /* Enable HW cache init */
>         temp = temp & ~MIPS_CTL0_CACHE_HW_INIT_INHIBIT;
>         /* deassert reset */
> --
> 2.43.0
>

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