Re: [PATCH] lib: sbi_domain_context: Flush TLB after SATP mode switch
Anup Patel <[email protected]> Tue, 9 Jun 2026 23:22:38 +0530
| Newsgroups | org.infradead.lists.opensbi |
|---|---|
| Message-ID | <CAAhSdy3p5yDAdfi4tto8gcDs+-cRds=y4d8hWBdJTpEYfEeqBw@mail.gmail.com> |
On Wed, Apr 29, 2026 at 11:48 PM Zishun Yi <[email protected]> wrote: > > When switching between domains with different satp.MODE values (e.g. > Sv39 to Sv48), the RISC-V ISA permits hardware to use cached > translations from the old virtual-address width if no SFENCE.VMA > intervenes. This constrained-unpredictable behavior is clarified in > riscv-isa-manual PR #2219. > > Add __sbi_sfence_vma_all() after the csr_swap(CSR_SATP, ...) in > switch_to_next_domain_context() to ensure translations from the new > domain's address width are used. > > Link: https://github.com/riscv/riscv-isa-manual/pull/2219 The hart protection re-configuration will anyway perform full sfence / hfence so instead of adding yet another sfence over here it will be better to move the hart protection re-configuration after the CSR+FP+Vector context switch. I will update the commit description and do the required code movement at the time of merging this patch. Reviewed-by: Anup Patel <[email protected]> Applied this patch to the riscv/opensbi repo. Thanks, Anup -- opensbi mailing list [email protected] http://lists.infradead.org/mailman/listinfo/opensbi