[PATCH] pci: pcie_dw_rockchip: add PCIe reset configuration delay

PCIe r6.0 sec 6.6.1 requires a 100 ms delay before the first
Configuration Request.

For ports supporting up to 5.0 GT/s, the delay is measured from
the end of Conventional Reset. For faster ports, it is measured
from the end of Link Training.

The Rockchip DesignWare PCIe driver currently deasserts PERST# and
proceeds after Link Training without guaranteeing these delays.
A fast-training endpoint may therefore receive its first
Configuration Request too early.

Apply the required delay according to the maximum supported link
speed.

This fixes PCIe enumeration of a MAXIO MAP1202 NVMe device on an
Orange Pi 5 (RK3588S), where enumeration was timing-sensitive and
could hang without the additional delay.

Signed-off-by: Oleg Kombarov <[email protected]>
---
 drivers/pci/pcie_dw_rockchip.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c
index 61117fa95e6..322b0be9771 100644
--- a/drivers/pci/pcie_dw_rockchip.c
+++ b/drivers/pci/pcie_dw_rockchip.c
@@ -267,6 +267,14 @@ static int rk_pcie_link_up(struct rk_pcie *priv)
 	mdelay(100);
 	if (dm_gpio_is_valid(&priv->rst_gpio))
 		dm_gpio_set_value(&priv->rst_gpio, 1);
+	/*
+	 * PCIe r6.0 sec 6.6.1 requires a 100 ms delay before the first
+	 * Configuration Request. For ports supporting up to 5.0 GT/s, measure
+	 * the delay from the end of Conventional Reset. For faster ports,
+	 * measure it from the end of Link Training.
+	 */
+	if (priv->gen <= LINK_SPEED_GEN_2)
+		mdelay(100);
 
 	/* Check if the link is up or not */
 	for (retries = 0; retries < 10; retries++) {
@@ -282,6 +290,9 @@ static int rk_pcie_link_up(struct rk_pcie *priv)
 		return -EIO;
 	}
 
+	if (priv->gen > LINK_SPEED_GEN_2)
+		mdelay(100);
+
 	dev_info(priv->dw.dev, "PCIe Link up, LTSSM is 0x%x\n",
 		 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
 	rk_pcie_debug_dump(priv);

---
base-commit: 527115ef6783cec49e5610c523c124b399011361
change-id: 20260814-pci-rockchip-perst-delay-998233a71fb1

Best regards,
--  
Oleg Kombarov <[email protected]>