[PATCH v6 2/4] arm64: dts: qcom: sm8550: add UART11 node
Alexandre Hamamdjian <[email protected]>
| Newsgroups | org.kernel.feeds.b4-sent,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Add the QUPv3_2 SE3 UART (UART11) controller node and its default pinctrl state to sm8550.dtsi, so boards with a peripheral wired to that serial engine can enable it through &uart11. The serial engine at 0x88c000 is already described as i2c11 and spi11, so the UART node takes the same qup_opp_table_120mhz they use: it is the same block behind the same GCC_QUPV3_WRAP2_S3_CLK, and its core clock tops out at 120 MHz rather than the 100 MHz the other table allows. TX and RX are biased pull-up, matching qup_uart14_default, so the lines idle high on boards that do not fit external pull-ups. Signed-off-by: Alexandre Hamamdjian <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 0e701e709235..fcbcf22ff951 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1442,6 +1442,24 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, status = "disabled"; }; + uart11: serial@88c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart11_default>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "qup-core", "qup-config"; + operating-points-v2 = <&qup_opp_table_120mhz>; + power-domains = <&rpmhpd RPMHPD_CX>; + status = "disabled"; + }; + i2c12: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; @@ -5478,6 +5496,14 @@ qup_uart7_default: qup-uart7-default-state { bias-disable; }; + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins = "gpio70", "gpio71"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + qup_uart14_default: qup-uart14-default-state { /* TX, RX */ pins = "gpio78", "gpio79"; -- 2.55.0