[MODERATED] Re: [patch V5 09/14] MDS basics 9

On Fri, Mar 01, 2019 at 05:03:39PM +0100, speck for Thomas Gleixner wrote:
> On Fri, 1 Mar 2019, speck for Josh Poimboeuf wrote:
> > On Wed, Feb 27, 2019 at 04:09:48PM +0100, speck for Thomas Gleixner wrote:
> > > Subject: [patch V5 09/14] x86/speculation/mds: Conditionally clear CPU buffers on idle entry
> > > From: Thomas Gleixner <[email protected]>
> > > 
> > > Add a static key which controls the invocation of the CPU buffer clear
> > > mechanism on idle entry. This is independent of other MDS mitigations
> > > because the idle entry invocation to mitigate the potential leakage due to
> > > store buffer repartitioning is only necessary on SMT systems.
> > > 
> > > Add the actual invocations to the different halt/mwait variants which
> > > covers all usage sites. mwaitx is not patched as it's not available on
> > > Intel CPUs.
> > > 
> > > The buffer clear is only invoked before entering the C-State to prevent
> > > that stale data from the idling CPU is spilled to the Hyper-Thread sibling
> > > after the Store buffer got repartitioned and all entries are available to
> > > the non idle sibling.
> > 
> > Andrea brought up a good question privately -- this patch mitigates
> > MSBDS for HT, but HT will still be susceptible to the other two MDS
> > issues.  So what's the point?  It seems this patch only protects people
> > who don't care about MDS in the first place.
> 
> Indeed for most CPU models it's pointless.
> 
> The ones which are only affected by MSBDS are Atom Silvermont/Airmont which
> are all single threaded and the XEON PHIs.
> 
> For XEON PHI it actually makes sense because XEON PHI does not have L1TF
> either.
> 
> But yes, for everything else it's just window dressing.

Makes sense.  I didn't realize that some CPUs were affected by MSBDS and
not other MDSes.

Can you add that justification to the documentation and/or patch
description?

-- 
Josh