[MODERATED] Re: [PATCH 3/9] TAA 3

On Thu, Oct 24, 2019 at 10:05:58PM +0200, speck for Borislav Petkov wrote:
> On Thu, Oct 24, 2019 at 02:59:59PM -0500, speck for Josh Poimboeuf wrote:
> > But pre-TSX_CTRL CPUs won't reach the above code, because of the
> > tsx_ctrl_is_supported() check at the beginning of tsx_init().
> 
> Yes, pre-TSX_CTRL won't have those CPUID bits cleared because they
> cannot anyway - MSR is not there.
> 
> And even if we clear the corresponding X86_FEATURE_ bits, nothing is
> stopping people from using TSX - they won't query /proc/cpuinfo but
> CPUID directly. Hell, they can even try the instructions and see if they
> fault or not, without querying any feature bits.
> 
> > And post-TSX_CTRL CPUs will have the HLE bit already cleared by
> > microcode.
> 
> Yes.
> 
> In both cases, the X86_FEATURE_* bits mirror what's in CPUID. At least
> for the two TSX bits: HLE and RTM.

Actually, according to the patches, with TSX_CTRL CPUs, HLE is
unconditionally disabled, but still enumerated as present in CPUID
(why???)

If that's the case then it sounds like X86_FEATURE_HLE needs to be
forced clear for TSX_CTRL CPUs?

-- 
Josh