[MODERATED] Re: [PATCH 3/9] TAA 3

On Thu, Oct 24, 2019 at 09:45:03PM +0200, speck for Borislav Petkov wrote:
> On Thu, Oct 24, 2019 at 06:39:35PM +0100, speck for Andrew Cooper wrote:
> > On 23/10/2019 10:01, speck for Pawan Gupta wrote:
> > > +	if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
> > > +		tsx_disable();
> > > +
> > > +		/*
> > > +		 * tsx_disable() will change the state of the
> > > +		 * RTM CPUID bit.  Clear it here since it is now
> > > +		 * expected to be not set.
> > > +		 */
> > > +		setup_clear_cpu_cap(X86_FEATURE_RTM);
> > 
> > This same argument applies to HLE, and it would be weird for
> > pre-TSX_CTRL CPUs with tsx=off to report HLE but not RTM in /proc/cpuid
> 
> Right, the correct fix for that would be to run tsx_init() before we
> read CPUID leafs in get_cpu_cap() because then it'll load the proper
> bits already and we won't have to clear anything - the MSR write
> would've cleared both CPUID bits already.
> 
> I just checked that it happens globally even:
> 
> $ ./cpuid -r | grep -E "^\s+0x00000007" | awk '{ print $6 }' | uniq
> edx=0xbc000400
> 
> Bits 4 (HLE) and 11 (RTM) are cleared on all CPUs.
> 
> I'll try this tomorrow to check whether it would even work that early.
> 
> If there's issues with it, then we'll have to do the above thing and
> clear HLE too, by hand.

But pre-TSX_CTRL CPUs won't reach the above code, because of the
tsx_ctrl_is_supported() check at the beginning of tsx_init().

And post-TSX_CTRL CPUs will have the HLE bit already cleared by
microcode.

-- 
Josh