Re: [PATCH v5 08/11] TAAv5 8

On Thu, 17 Oct 2019, speck for Pawan Gupta wrote:
> On Wed, Oct 16, 2019 at 02:15:08PM +0200, speck for Thomas Gleixner wrote:
> Below is the matrix for the impact of tsx=<on|off|auto> cmdline options
> on state of TAA mitigation, VERW behavior and TSX feature for various
> combinations of MSR_IA32_ARCH_CAPABILITIES bits.
> 
> 1. tsx=auto
> +----------+----------+----------------+---------------+--------------+-------------------+
> |  MSR_IA32_ARCH_CAPABILITIES bits     |           Result with cmdline tsx=auto           |
> +----------+----------+----------------+---------------+--------------+-------------------+
> |  TAA_NO  |  MDS_NO  |  TSX_CTRL_MSR  |  VERW clears  |  TSX state   |  TAA mitigation   |
> |          |          |                |  CPU buffers  | after bootup |                   |
> +==========+==========+================+===============+==============+===================+
> |    0     |    0     |       0        |      Yes      |  HW default  |    Same as MDS    |
> +----------+----------+----------------+---------------+--------------+-------------------+
> |    0     |    0     |       1        | Invalid case  | Invalid case |   Invalid case    |
> +----------+----------+----------------+---------------+--------------+-------------------+

So you're saying that if TSX_CTRL_MSR is available VERW clears CPU buffers
independent of MDS_NO being set, right? So:

  MDS_NO	MD_CLEAR	TSX_CTRL_MSR
    0		  0		    0		Vulnerable (needs ucode)
    0		  1		    0		MDS and TAA mitigated via VERW
    1		  1		    0		MDS fixed, TAA vulnerable if TSX enabled
    		  		    		because MD_CLEAR has no meaning and
						VERW is not guaranteed to clear buffers
    1		  x		    1		MDS fixed, TAA can be mitigated by
    		  		    		    	   VERW or TSX_CTRL_MSR

If so, please document all of that proper and fixup the other comments
people had on this series.

Thanks,

	tglx