[MODERATED] Re: [PATCH 3/9] TAA 3

> >> On Haswell and Broadwell, the microcode which turned HLE/RTM off in the
> >> pipeline left the LBR MSRs in a state where you can't context switch the
> >> value, because they would yield a value via RDMSR which WRMSR faulted
> >> on, because the two operations had an asymmetric view of how the top
> >> bits of metadata should be interpreted, given some TSX-related metadata
> >> and a sign extended linear address.
> >>
> >> On Skylake where you can't actually turn RTM off, but we may hide
> >> FEATURE_RTM/HLE, the above quirk is probably not true.
> > Huh? How is that possible? TSX_CTRL has defined only bit 1 there, the CPUID
> > enumeration bit, and bit 0 doesn't do any RTM disabling? Srsly?!
> 
> Skylake CPUs aren't getting TSX_CTRL, but force setting/clearing bits at
> boot will affect later logic.  (Unless I'm being blind while reading the
> patches, which is a distinct possibility).

tsx_init() will not force bits at boot on Skylake because of
tsx_ctrl_is_supported() check.

Would adding this comment help?

----
diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c
index 0969e6e9dff3..416dad3b8590 100644
--- a/arch/x86/kernel/cpu/tsx.c
+++ b/arch/x86/kernel/cpu/tsx.c
@@ -78,9 +78,19 @@ static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
 
 void __init tsx_init(void)
 {
	char arg[5] = {};
 	int ret;
 
+	/*
+	 * On MDS_NO=0 CPUs tsx_init() would do nothing and simply return from
+	 * here.
+	 *
+	 * TSX control(aka MSR_IA32_TSX_CTRL) is only available after a
+	 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
+	 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
+	 * MSR_IA32_TSX_CTRL even after the microcode update. tsx= cmdline
+	 * requests will do nothing on CPUs without MSR_IA32_TSX_CTRL support.
+	 */
 	if (!tsx_ctrl_is_supported())
 		return;