[MODERATED] Re: [PATCH v5 05/11] TAAv5 5

On Fri, Oct 04, 2019 at 11:30:31PM -0700, speck for Pawan Gupta wrote:
> TSX Async Abort (TAA) is a side channel vulnerability to the internal
> buffers in some Intel processors similar to Microachitectural Data
> Sampling (MDS).  In this case certain loads may speculatively pass
> invalid data to dependent operations when an asynchronous abort
> condition is pending in a TSX transaction.  This includes loads with no
> fault or assist condition.  Such loads may speculatively expose stale
> data from the uarch data structures as in MDS.  Scope of exposure is
> within the same-thread and cross-thread.  This issue affects all current
> processors that support TSX, but do not have ARCH_CAP_TAA_NO (bit 8) set
> in MSR_IA32_ARCH_CAPABILITIES.

All the patches are missing "Subject:" lines, so when applied, they have
subjects like "TAAv5 1".

> -/* Update the static key controlling the MDS CPU buffer clear in idle */
> +/* Update the static key controlling the MDS and TAA CPU buffer clear in idle */
>  static void update_mds_branch_idle(void)
>  {
>  	/*
> @@ -775,8 +881,11 @@ static void update_mds_branch_idle(void)
>  	 * The other variants cannot be mitigated when SMT is enabled, so
>  	 * clearing the buffers on idle just to prevent the Store Buffer
>  	 * repartitioning leak would be a window dressing exercise.
> +	 *
> +	 * Apply idle buffer clearing to TAA affected CPUs also.
>  	 */
> -	if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
> +	if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY) &&
> +	    !boot_cpu_has_bug(X86_BUG_TAA))
>  		return;

I'm not sure this belongs here.  The existing check was for
X86_BUG_MSBDS_ONLY, which is the only MDS variant which can be mitigated
in idle with SMT enabled.  If the other MDS variants are present (which
is true for most CPUs) then this function doesn't enable the MDS idle
mitigation, because it wouldn't be sufficient.

So does this fully mitigate TAA on idle threads with SMT enabled?  If
not then this change is probably pointless.

-- 
Josh