[MODERATED] Re: [PATCH 3/9] TAA 3
Andrew Cooper <[email protected]>
| Newsgroups | org.kernel.lore.historical-speck |
|---|---|
| Message-ID | <[email protected]> |
On 24/10/2019 21:36, speck for Borislav Petkov wrote: > On Thu, Oct 24, 2019 at 03:14:03PM -0500, speck for Josh Poimboeuf wrote: >> Actually, according to the patches, with TSX_CTRL CPUs, HLE is >> unconditionally disabled, but still enumerated as present in CPUID >> (why???) > I found it: in an older email thread Andrew talks about migration > compatibility and HLE. Dunno if we care but maybe someone else has a > better idea. The first TSX problem in Haswell/Broadwell lead to chaos when a microcode update took feature bits out. When the second problem came around, I understand from IRL conversations that several vendors firmly expressed their opinion about whether feature bits should disappear in microcode. As HLE is a hint bit at best, it was left visible despite being disabled behind the scenes. ~Andrew