[MODERATED] Re: [PATCH 7/9] TAA 7
Borislav Petkov <[email protected]> Thu, 24 Oct 2019 21:53:16 +0200
| Newsgroups | org.kernel.lore.historical-speck |
|---|---|
| Message-ID | <[email protected]> |
On Thu, Oct 24, 2019 at 08:20:42PM +0200, speck for Jiri Kosina wrote:
> On Thu, 24 Oct 2019, speck for Borislav Petkov wrote:
>
> > "Disable TSX if the CPU is affected by the TSX Async Abort (TAA)
> > vulnerability and microcode provides a special MSR - TSX_CTRL_MSR -
> > which provides the required TSX control knobs. On MDS-affected parts
> > where VERW takes care of the TAA vulnerability, that controlling MSR is
> > not present and thus TSX cannot be disabled there."
>
> This is true if you ignore hyperthreading.
>
> On SMT systems, TSX disable is 100% complete mitigation, while VERW
> clearing is not.
So why is our default this then?
static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
and we only do the TAA_MITIGATION_TSX_DISABLED thing only if TSX has
been disabled earlier?
Because of those MDS_NO=0 machines which don't get the TSX_CTRL MSR so
that TSX cannot be disabled there?
Are some of those machines SMT?
Because if so, we *must* disable SMT unconditionally to mitigate TAA
completely there... methinks.
--
Regards/Gruss,
Boris.
SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG Nürnberg