[MODERATED] Re: [PATCH 3/9] TAA 3

On Thu, Oct 24, 2019 at 11:38:21PM +0100, speck for Andrew Cooper wrote:
> I don't necessarily disagree, but the customers (who ultimately pay my
> salary) want late microcode loading and livepatching, so we've delivered.

Yeah, you guys promised too much. How do you deal with userspace using
a feature and you wanna upgrade microcode which disables it? TSX might
not be a good example here because feature bits disappearing is still ok,
it doesn't fault but it would simply start aborting transactions
unconditionally but what if it is a CPU feature which userspace is
actively using and it disappears underneath its feet all of a sudden?

Just upgrade the microcode and forget about it is not enough. I'm pretty
sure you'll have to "dance". But hey, you can buy almost everything with
money nowadays so... :-)

> Skylake CPUs aren't getting TSX_CTRL, but force setting/clearing bits at
> boot will affect later logic.  (Unless I'm being blind while reading the
> patches, which is a distinct possibility).

Yes, that's why I'm saying we should not blindly force set and clear
bits but mirror what CPUID is telling us. At least wrt TSX.

-- 
Regards/Gruss,
    Boris.

SUSE Software Solutions Germany GmbH, GF: Felix Imendörffer, HRB 36809, AG Nürnberg
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