[PATCH/RFC 9/9] arm64: dts: renesas: ironhide: Switch to pure SCMI

Geert Uytterhoeven <[email protected]>
Newsgroups org.kernel.vger.arm-scmi,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pm,org.kernel.vger.linux-renesas-soc
Message-ID <0940352910d97e24410c5fffd815a8dded3db070.1781171706.git.geert+renesas@glider.be>
Switch from CPG/MDLC remapping to pure SCMI:
  - Add SCMI IDs for selected devices, supporting SCP FW SDK v4.28,
    v4.31, and v4.32,
  - Enable SCMI clock domain support,
  - Replace clocks, power-domains, and resets properties by pure SCMI
    references.

Note that the user must uncomment the line that defines
R_CAR_X5H_SCP_FW_SDK_VERSION to the SCP FW SDK version being used.

Signed-off-by: Geert Uytterhoeven <[email protected]>
---
This patch is included as a PoC.
This fails to apply, as the SCMI protocol subnodes are not added in this
series.
---
 .../boot/dts/renesas/r8a78000-ironhide.dts    | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
index 00b5a010b7247722..f4093c359b21379e 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -9,6 +9,45 @@
 #include <dt-bindings/soc/renesas,r8a78000-mfis.h>
 #include "r8a78000.dtsi"
 
+#define V4_28	4028
+#define V4_31	4031	// Supports v4.31 and v4.32
+
+//#define R_CAR_X5H_SCP_FW_SDK_VERSION	V4_28
+#define R_CAR_X5H_SCP_FW_SDK_VERSION	V4_31
+
+#if R_CAR_X5H_SCP_FW_SDK_VERSION == V4_28
+
+#define CLK_SGD4_PERW_BUS	1661
+#define MDLC_HSCIF0		228
+#define MDLC_HSCIF1		229
+#define MDLC_SCIF0		209
+#define MDLC_SCIF1		210
+#define MDLC_UFS1		203
+#define RESET_HSCIF0		228
+#define RESET_HSCIF1		229
+#define RESET_SCIF0		209
+#define RESET_SCIF1		210
+#define RESET_UFS1		203
+
+#elif R_CAR_X5H_SCP_FW_SDK_VERSION == V4_31
+
+#define CLK_SGD4_PERW_BUS	1657
+#define MDLC_HSCIF0		224
+#define MDLC_HSCIF1		225
+#define MDLC_SCIF0		205
+#define MDLC_SCIF1		206
+#define MDLC_UFS1		199
+#define RESET_HSCIF0		224
+#define RESET_HSCIF1		225
+#define RESET_SCIF0		205
+#define RESET_SCIF1		206
+#define RESET_UFS1		199
+
+#endif
+
+#define PD_APL			257
+#define PD_UFS1			13
+
 / {
 	model = "Renesas Ironhide board based on r8a78000";
 	compatible = "renesas,ironhide", "renesas,r8a78000";
@@ -35,6 +74,7 @@ scmi: scmi {
 			scmi_devpd: protocol@11 {
 				reg = <0x11>;
 				#power-domain-cells = <1>;
+				arm,clock-domain = <&scmi_clk>;
 			};
 
 			scmi_sys: protocol@12 {
@@ -138,6 +178,10 @@ &extalr_clk {
 };
 
 &hscif0 {
+	clocks = <&scmi_clk MDLC_HSCIF0>, <&scmi_clk CLK_SGD4_PERW_BUS>,
+		 <&scif_clk>;
+	power-domains = <&scmi_devpd PD_APL>;
+	resets = <&scmi_reset RESET_HSCIF0>;
 	uart-has-rtscts;
 	status = "okay";
 };
-- 
2.43.0
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