[PATCH 32/45] clk: socfpga: Make sure clk_init_data is fully initialized
Geert Uytterhoeven <[email protected]>
| Newsgroups | org.kernel.vger.arm-scmi,dev.linux.lists.imx,dev.linux.lists.linux-sunxi,dev.linux.lists.soc,org.infradead.lists.linux-mediatek,org.kernel.vger.linux-clk,org.kernel.vger.linux-kernel,org.kernel.vger.linux-mips,org.kernel.vger.linux-renesas-soc,org.kernel.vger.linux-samsung-soc,org.kernel.vger.linux-tegra,org.ozlabs.lists.linux-aspeed,org.ozlabs.lists.openbmc |
|---|---|
| Message-ID | <2d38d78f8d59583e29778bebc65eaab911d8a120.1787239813.git.geert+renesas@glider.be> |
The clk_init_data structure contains several mutually-exclusive members for different methods to specify the possible parents of a clock, prompting drivers to initialize only the members they need. However, not initializing all members may cause subtle issues, which are only exposed when CONFIG_INIT_STACK_ALL_PATTERN or CONFIG_INIT_STACK_NONE is enabled. Make sure all members are fully initialized, to avoid such bugs, and to prevent future breakage when converting drivers to a different method for specifying the parents. Signed-off-by: Geert Uytterhoeven <[email protected]> --- Compile-tested only. --- drivers/clk/socfpga/clk-gate-a10.c | 2 +- drivers/clk/socfpga/clk-gate-s10.c | 6 +++--- drivers/clk/socfpga/clk-gate.c | 2 +- drivers/clk/socfpga/clk-periph-a10.c | 2 +- drivers/clk/socfpga/clk-periph-s10.c | 8 ++++---- drivers/clk/socfpga/clk-periph.c | 2 +- drivers/clk/socfpga/clk-pll-a10.c | 2 +- drivers/clk/socfpga/clk-pll-s10.c | 8 ++++---- drivers/clk/socfpga/clk-pll.c | 2 +- 9 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index dd8d1713aaff7639..ba12179061b3fe9d 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -49,7 +49,7 @@ static void __init __socfpga_gate_init(struct device_node *node, struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; int rc; socfpga_clk = kzalloc_obj(*socfpga_clk); diff --git a/drivers/clk/socfpga/clk-gate-s10.c b/drivers/clk/socfpga/clk-gate-s10.c index 24f56a9edc44e528..4b23909c58106599 100644 --- a/drivers/clk/socfpga/clk-gate-s10.c +++ b/drivers/clk/socfpga/clk-gate-s10.c @@ -128,7 +128,7 @@ struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void _ { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *parent_name = clks->parent_name; int ret; @@ -186,7 +186,7 @@ struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, voi { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *parent_name = clks->parent_name; int ret; @@ -244,7 +244,7 @@ struct clk_hw *agilex5_register_gate(const struct agilex5_gate_clock *clks, void { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; - struct clk_init_data init; + struct clk_init_data init = {}; int ret; socfpga_clk = kzalloc_obj(*socfpga_clk); diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index ced8e09884068a26..d0f9fa44ad182520 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -143,7 +143,7 @@ void __init socfpga_gate_init(struct device_node *node) struct socfpga_gate_clk *socfpga_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; struct clk_ops *ops; int rc; diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index 4eb5787f0dea3f8e..8aefc58ba4ec3944 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -65,7 +65,7 @@ static void __init __socfpga_periph_init(struct device_node *node, struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; int rc; u32 fixed_div; u32 div_reg[3]; diff --git a/drivers/clk/socfpga/clk-periph-s10.c b/drivers/clk/socfpga/clk-periph-s10.c index 5195b9476da16977..dc923d0d87869743 100644 --- a/drivers/clk/socfpga/clk-periph-s10.c +++ b/drivers/clk/socfpga/clk-periph-s10.c @@ -103,7 +103,7 @@ struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks, { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; const char *parent_name = clks->parent_name; int ret; @@ -139,7 +139,7 @@ struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks, { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; const char *parent_name = clks->parent_name; int ret; @@ -174,7 +174,7 @@ struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *c { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; const char *parent_name = clks->parent_name; int ret; @@ -220,7 +220,7 @@ struct clk_hw *agilex5_register_cnt_periph(const struct agilex5_perip_cnt_clock { struct clk_hw *hw_clk; struct socfpga_periph_clk *periph_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index 3821db6777e75413..8fa3d8e20042d731 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -55,7 +55,7 @@ static void __init __socfpga_periph_init(struct device_node *node, struct socfpga_periph_clk *periph_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; int rc; u32 fixed_div; u32 div_reg[3]; diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index c56f276e8d51e00f..63b8b75045aead8d 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -71,7 +71,7 @@ static void __init __socfpga_pll_init(struct device_node *node, struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFGPA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; struct device_node *clkmgr_np; int rc; int i = 0; diff --git a/drivers/clk/socfpga/clk-pll-s10.c b/drivers/clk/socfpga/clk-pll-s10.c index ee236e87da33c020..1dca54b48375b168 100644 --- a/drivers/clk/socfpga/clk-pll-s10.c +++ b/drivers/clk/socfpga/clk-pll-s10.c @@ -192,7 +192,7 @@ struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; @@ -232,7 +232,7 @@ struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; @@ -271,7 +271,7 @@ struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; @@ -310,7 +310,7 @@ struct clk_hw *agilex5_register_pll(const struct agilex5_pll_clock *clks, { struct clk_hw *hw_clk; struct socfpga_pll *pll_clk; - struct clk_init_data init; + struct clk_init_data init = {}; const char *name = clks->name; int ret; diff --git a/drivers/clk/socfpga/clk-pll.c b/drivers/clk/socfpga/clk-pll.c index f85adb16d414040f..aa13cc9d6db115fe 100644 --- a/drivers/clk/socfpga/clk-pll.c +++ b/drivers/clk/socfpga/clk-pll.c @@ -78,7 +78,7 @@ static void __init __socfpga_pll_init(struct device_node *node, struct socfpga_pll *pll_clk; const char *clk_name = node->name; const char *parent_name[SOCFPGA_MAX_PARENTS]; - struct clk_init_data init; + struct clk_init_data init = {}; struct device_node *clkmgr_np; int rc; -- 2.43.0