[PATCH V3 1/2] schemas: pci: bridge: Document PCI L0s & L1 entry delay
Krishna Chaitanya Chundru <[email protected]>
| Newsgroups | org.kernel.vger.devicetree-spec,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-pci |
|---|---|
| Message-ID | <[email protected]> |
Some controllers and endpoints provide provision to program the entry delays of L0s & L1 which will allow the link to enter L0s & L1 more aggressively to save power. These values needs to be programmed before link training. Signed-off-by: Krishna Chaitanya Chundru <[email protected]> --- dtschema/schemas/pci/pci-bus-common.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml index 94b648f..a9309af 100644 --- a/dtschema/schemas/pci/pci-bus-common.yaml +++ b/dtschema/schemas/pci/pci-bus-common.yaml @@ -150,6 +150,12 @@ properties: description: Disables ASPM L0s capability type: boolean + aspm-l0s-entry-delay-ns: + description: ASPM L0s entry delay + + aspm-l1-entry-delay-ns: + description: ASPM L1 entry delay + vpcie12v-supply: description: 12v regulator phandle for the slot -- 2.34.1