Re: [PATCH v1 2/3] dmaengine: dw-edma: Enable Chan Separation via VSEC

On 22-Jul-26 20:30, Frank Li wrote:
> On Wed, Jul 22, 2026 at 04:46:39PM +0530, Devendra K Verma wrote:
>> As per, 'Designware Cores PCI Express DM Controller - Reference
>> Manual', section 3.2.34.3, VSEC for DEVICE INFORMATION supports
>> the channel separation mechanisms. Basically, the HDMA IP allows
>> the user to configure the separation between DMA channel
>> registers and retrieve it via the VSEC capability mentioned
>> above.
>>
>> HDMA IP supports the channel separation up to 32K but for
>> the simplicity channel separation support has been added till
>> 4K. As and when required the function can be expanded to include
>> the higher sizes for channel separation.
>> Supported and missed out sizes are:
>> 8K (0x5), 16K (0x6), 32K (0x7)
>>
>> Signed-off-by: Devendra K Verma <[email protected]>
>> ---
>>   drivers/dma/dw-edma/dw-edma-pcie.c | 25 +++++++++++++++++++++++--
>>   1 file changed, 23 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c
>> index ec5e057a0f11..6295d01ba2f7 100644
>> --- a/drivers/dma/dw-edma/dw-edma-pcie.c
>> +++ b/drivers/dma/dw-edma/dw-edma-pcie.c
>> @@ -33,6 +33,7 @@
>>   #define DW_PCIE_XILINX_VSEC_ID			0x20
>>   #define DW_PCIE_XILINX_VSEC_DMA_BAR		GENMASK(10, 8)
>>   #define DW_PCIE_XILINX_VSEC_DMA_MAP		GENMASK(2, 0)
>> +#define DW_PCIE_XILINX_VSEC_CH_SEP		GENMASK(18, 16)
> 
> Can keep as bit pos order for the same register?
> 
>>   #define DW_PCIE_XILINX_VSEC_DMA_WR_CH		GENMASK(9, 0)
>>   #define DW_PCIE_XILINX_VSEC_DMA_RD_CH		GENMASK(25, 16)
>>
>> @@ -73,6 +74,7 @@ struct dw_edma_pcie_data {
>>   	u16				wr_ch_cnt;
>>   	u16				rd_ch_cnt;
>>   	u64				devmem_phys_off;
>> +	u32				ch_sep_sz;
>>   };
>>
>>   static const struct dw_edma_pcie_data snps_edda_data = {
>> @@ -127,7 +129,7 @@ static const struct dw_edma_pcie_data xilinx_mdb_data = {
>>   };
>>
>>   static const struct dw_edma_pcie_data xilinx_cpm6_dma_data = {
>> -	/* MDB registers location */
>> +	/* CPM6 registers location */
>>   	.rg.bar				= BAR_0,
>>   	.rg.off				= SZ_4K,	/*  4 Kbytes */
>>   	.rg.sz				= SZ_8K,	/*  8 Kbytes */
>> @@ -189,6 +191,23 @@ static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)
>>   	return pci_irq_vector(to_pci_dev(dev), nr);
>>   }
>>
>> +static u32 dw_edma_get_ch_sep_sz(u32 ch_sep_val)
>> +{
>> +	switch (ch_sep_val) {
>> +	default:
>> +	case 0:
>> +		return 256;
>> +	case 1:
>> +		return 512;
>> +	case 2:
>> +		return 1024;
>> +	case 3:
>> +		return 2048;
>> +	case 4:
>> +		return 4096;
>> +	}
> 
> 	256 << ch_sep_val ?
> 

Thank you for this suggestion.

> 
>> +}
>> +
>>   static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr)
>>   {
>>   	struct pci_dev *pdev = to_pci_dev(dev);
>> @@ -278,6 +297,8 @@ static void dw_edma_pcie_get_xilinx_dma_data(struct pci_dev *pdev,
>>
>>   	pdata->mf = map;
>>   	pdata->rg.bar = FIELD_GET(DW_PCIE_XILINX_VSEC_DMA_BAR, val);
>> +	pdata->ch_sep_sz = dw_edma_get_ch_sep_sz(FIELD_GET(DW_PCIE_XILINX_VSEC_CH_SEP,
>> +							   val));
>>
>>   	pci_read_config_dword(pdev, vsec + 0xc, &val);
>>   	pdata->wr_ch_cnt = min(pdata->wr_ch_cnt,
>> @@ -324,9 +345,9 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev,
>>   	struct dw_edma_pcie_data *pdata = (void *)pid->driver_data;
>>   	struct device *dev = &pdev->dev;
>>   	struct dw_edma_chip *chip;
>> +	bool non_ll = false;
>>   	int err, nr_irqs;
>>   	int i, mask;
>> -	bool non_ll = false;
> 
> unnessary change here.
> 
> Frank

Just wanted to maintain the inverted X-tree formatting.
Missed this in the previous submitted patch series.

>>
>>   	if (!pdata)
>>   		return -ENODEV;
>> --
>> 2.43.0
>>