Re: [PATCH 8/9] spi: dw: Use dma_slave_caps bus width helpers

Thank you for your contribution! Sashiko AI review found 1 potential issue(=
s) to consider:

Pre-existing issues:
- [High] `dw_spi_can_dma` relies on a stale `dws->n_bytes` value, which may=
 cause incorrect DMA fallback or unsupported DMA configuration.
--

--- Patch [8]: [PATCH 8/9] spi: dw: Use dma_slave_caps bus width helpers ---
commit cd2773a5f68d147fd25b2ce32d4b2dd68d630ea4
Author: Nuno S=C3=A1 <[email protected]>

spi: dw: Use dma_slave_caps bus width helpers

Store the common TX destination and RX source bus widths in a driver-owned
DMA bus width bitmap and populate it through the dma_slave_caps helper.
This avoids depending on the legacy addr_widths masks.

> diff --git a/drivers/spi/spi-dw-dma.c b/drivers/spi/spi-dw-dma.c
> index fe726b9b1780d..2e23ead4a94f9 100644
> --- a/drivers/spi/spi-dw-dma.c
> +++ b/drivers/spi/spi-dw-dma.c
[ ... ]
> @@ -253,7 +253,7 @@ static bool dw_spi_can_dma(struct spi_controller *ctl=
r,
> =20
>  	dma_bus_width =3D dw_spi_dma_convert_width(dws->n_bytes);
> =20

[Severity: High]
This is a pre-existing issue, but does dw_spi_can_dma() rely on a stale
dws->n_bytes value here?

The dws->n_bytes field holds the word size of the previous transfer. Should
dw_spi_can_dma() compute the bus width directly from xfer->bits_per_word to
correctly evaluate the DMA capability for the current transfer?

If a device uses different bus widths for successive SPI transfers, an
earlier transfer might use a bus width supported by the DMA controller, but
a later transfer uses an unsupported width. This would cause
dw_spi_can_dma() to incorrectly allow the second transfer to be DMA mapped
because it checks the stale dws->n_bytes from the first transfer.

When the SPI core later executes dw_spi_transfer_one() for the second
transfer, dws->n_bytes is updated to the actual unsupported width, and
dw_spi_dma_setup() attempts to configure the DMA engine with it, causing
dmaengine_slave_config() to fail and aborting the transfer.

> -	return dws->dma_addr_widths & BIT(dma_bus_width);
> +	return test_bit(dma_bus_width, dws->dma_bus_widths);
>  }
> =20
>  static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 spe=
ed)

--=20
Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260730-dmaengine-=
[email protected]?part=3D8