Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] DMA_CYCLIC capability applied to wrong dma_device during initialization.
--
--- Patch [5]: [PATCH v2 05/13] dmaengine: ste_dma40: Fix LCLA allocation order ---
commit d327ef86f7f30a5a539d2fef537e53e5f0f2dc5f
Author: Linus Walleij <[email protected]>
dmaengine: ste_dma40: Fix LCLA allocation order
This commit modifies d40_lcla_allocate() to use get_order() to determine
the page allocation order, instead of directly passing the calculated
number of pages to __get_free_pages() and free_pages().
Closes: https://lore.kernel.org/dmaengine/[email protected]/
> diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
> index 384c2f3805b02..804eb5eab06b4 100644
> --- a/drivers/dma/ste_dma40.c
> +++ b/drivers/dma/ste_dma40.c
[ ... ]
> @@ -3670,7 +3669,7 @@ static int __init d40_probe(struct platform_device *pdev)
>
> if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
> free_pages((unsigned long)base->lcla_pool.base,
> - base->lcla_pool.pages);
> + base->lcla_pool.alloc_order);
>
> kfree(base->lcla_pool.base_unaligned);
>
[Severity: High]
This is a pre-existing issue, but I noticed a potential problem in
d40_dmaengine_init():
drivers/dma/ste_dma40.c:d40_dmaengine_init() {
...
d40_chan_init(base, &base->dma_both, base->phy_chans,
0, num_reserved_chans);
dma_cap_zero(base->dma_both.cap_mask);
dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
...
}
Does this code apply the DMA_CYCLIC capability to the wrong dma_device during
initialization?
By setting DMA_CYCLIC on base->dma_slave.cap_mask instead of
base->dma_both.cap_mask, the dma_both device seems to lack this capability.
Will this cause initialization failures for peripherals requesting a cyclic
channel from dma_both?
--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=5
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