[PATCH v2 3/4] arm64: dts: qcom: monaco: add RAS error source nodes
Umang Chheda <[email protected]>
| Newsgroups | org.kernel.vger.linux-acpi,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-edac,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Add RAS error source nodes for the Monaco SoC. Two processor error sources are described: a per-PE node covering the L1/L2 cache hierarchy using a PPI, and two shared L3 cache nodes for the two CPU clusters using SPIs. Co-developed-by: Faruque Ansari <[email protected]> Signed-off-by: Faruque Ansari <[email protected]> Signed-off-by: Umang Chheda <[email protected]> --- arch/arm64/boot/dts/qcom/monaco.dtsi | 30 ++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 64fc0d592282..4fbd1dc9a147 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -724,6 +724,36 @@ system_pd: power-domain-system { }; }; + ras-l1l2-0 { + compatible = "arm,ras-processor"; + arm,num-records = <1>; + arm,record-impl = /bits/ 64 <0x1>; + arm,status-reporting = /bits/ 64 <0x1>; + cache = <&l2_0>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "fhi"; + }; + + ras-l3-cluster0 { + compatible = "arm,ras-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x2>; + arm,status-reporting = /bits/ 64 <0x2>; + cache = <&l3_0>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fhi"; + }; + + ras-l3-cluster1 { + compatible = "arm,ras-processor"; + arm,num-records = <2>; + arm,record-impl = /bits/ 64 <0x2>; + arm,status-reporting = /bits/ 64 <0x2>; + cache = <&l3_1>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "fhi"; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; -- 2.34.1