Re: [PATCH v4 0/3] clk: ultrarisc: add DP1000 clock support
Brian Masney <[email protected]>
| Newsgroups | org.kernel.vger.linux-clk,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Hi Jia, On Mon, Jul 20, 2026 at 08:38:03AM +0800, Jia Wang via B4 Relay wrote: > This series exports a small common clock helper and adds the devicetree > binding and clock driver for the UltraRISC DP1000 SoC. > > The clock tree is driven by a SYSPLL and provides fixed-factor clocks for > the subsystem and PCIe, divider-based root clocks for GMAC and the UART, > I2C, and SPI blocks, and per-instance gate clocks for UART0-3, I2C0-3, > and SPI0-1. > > Testing: > - dt_binding_check and dtbs_check on ultrarisc,dp1000-clk > - Kernel build for RISC-V and boot-tested on DP1000 > - Modules build test for CLK_ULTRARISC_DP1000 > > Signed-off-by: Jia Wang <[email protected]> > --- > Changes in v4: > - Drop the initial clk_hw_get_rate() max-rate warning after setting the > divider rate range. I also see this in the diff between v3 and v4. Is this expected? +++ b/drivers/clk/ultrarisc/clk-dp1000.c @@ -0,0 +1,154 @@ @@ -309,8 +309,8 @@ + .frac_mask = GENMASK(23, 0), + .m_mask = GENMASK(23, 16), + .n_mask = GENMASK(11, 6), -+ .oddiv1_mask = GENMASK(4, 3), -+ .oddiv2_mask = GENMASK(1, 0), ++ .oddiv1_mask = GENMASK(1, 0), ++ .oddiv2_mask = GENMASK(4, 3), Brian