[PATCH v2 0/2] Fix RK3576/RK3588 fractional PLL rate calculation
Alexey Charkov <[email protected]>
| Newsgroups | org.kernel.vger.linux-clk,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-rockchip,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Fractional PLL rate recalculation for RK3576/RK3588 doesn't correspond to what the hardware actually does due to two issues: wrong denominator for the fractional component, and wrong signedness of the fractional component. The result is the kernel-visible PLL rate being off by about 2 MHz for the two affected PLL rates vs. what the hardware produces. While this fixes a real bug it's not a regression, as the issue was introduced in the same commit that added the RK3576/RK3588 support. Note that there is a separate unrelated issue with the rate table, namely the 2256000000 Hz entry currently leads to a VCO frequency of 4512 MHz, which is just above the TRM-stated maximum of 4500 MHz. Also multiple entries in the table end up with Fvco < 3 GHz, which according to the TRM leads to a PLL period jitter of +-2% vs. the +-1% for Fvco > 3 GHz. To be revisited and optimized separately. Signed-off-by: Alexey Charkov <[email protected]> --- Changes in v2: - Split out the denominator fix into its own patch (thanks Heiko) - Reword the commit description for clarity (thanks Quentin and Sebastian) - Add relevant clock derivation formulas and key constraints directly into a code comment for easier future reference - Link to v1: https://patch.msgid.link/[email protected] To: Michael Turquette <[email protected]> To: Stephen Boyd <[email protected]> To: Brian Masney <[email protected]> To: Heiko Stuebner <[email protected]> To: Elaine Zhang <[email protected]> To: Sebastian Reichel <[email protected]> To: Wyon Bi <[email protected]> To: Finley Xiao <[email protected]> To: Liang Chen <[email protected]> To: YouMin Chen <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Detlev Casanova <[email protected]> Cc: Dragan Simic <[email protected]> --- Alexey Charkov (2): clk: rockchip: pll: Fix the fractional part denominator on RK3588/RK3576 clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement drivers/clk/rockchip/clk-pll.c | 16 ++++++++++++---- drivers/clk/rockchip/clk-rk3576.c | 4 ++-- drivers/clk/rockchip/clk-rk3588.c | 4 ++-- drivers/clk/rockchip/clk.h | 8 ++++---- 4 files changed, 20 insertions(+), 12 deletions(-) --- base-commit: b4515cf4156356e8f4fe6e0fdc17f59adab9772f change-id: 20260721-rk3588-fracpll-f4377cd80983 Best regards, -- Alexey Charkov <[email protected]>