Re: [PATCH v2 4/6] clk: qcom: Add Nord display clock controller support
Taniya Das <[email protected]>
| Newsgroups | org.kernel.vger.linux-clk,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
On 7/22/2026 2:02 PM, Alexandre Mergnat wrote:
>> +
>> +static const u32 disp_cc_0_nord_critical_cbcrs[] = {
>> + 0xc00c, /* MDSS_DISP_CC_AHB_CLK */
>> + 0xc008, /* MDSS_DISP_CC_VSYNC_CLK */
> These two comments look mislabeled: offsets 0xc00c/0xc008 are the RSCC AHB/VSYNC
> clocks (cf. disp_cc_mdss_rscc_ahb_clk @0xc00c and disp_cc_mdss_rscc_vsync_clk @0xc008
> in dispcc-sm8550.c / dispcc-milos.c), whereas the plain AHB/VSYNC branches in this
> file are at 0x80c0 / 0x8030. dispcc1-nord.c labels these same offsets as RSCC.
> Can you double check and update them to MDSS_DISP_CC_RSCC_AHB_CLK and
> MDSS_DISP_CC_RSCC_VSYNC_CLK ?
> The offsets looks correct, only the comments differ.
Yes, Alexandra the comments are mislabeled. I will fix in the next patch.
--
Thanks,
Taniya Das