Re: [PATCH v2 0/2] Fix RK3576/RK3588 fractional PLL rate calculation

Hi Heiko,

On Thu, Jul 23, 2026 at 2:22 PM Alexey Charkov <[email protected]> wrote:
>
> Fractional PLL rate recalculation for RK3576/RK3588 doesn't correspond to
> what the hardware actually does due to two issues: wrong denominator for
> the fractional component, and wrong signedness of the fractional
> component. The result is the kernel-visible PLL rate being off by about
> 2 MHz for the two affected PLL rates vs. what the hardware produces.
>
> While this fixes a real bug it's not a regression, as the issue was
> introduced in the same commit that added the RK3576/RK3588 support.
>
> Note that there is a separate unrelated issue with the rate table, namely
> the 2256000000 Hz entry currently leads to a VCO frequency of 4512 MHz,
> which is just above the TRM-stated maximum of 4500 MHz. Also multiple
> entries in the table end up with Fvco < 3 GHz, which according to the
> TRM leads to a PLL period jitter of +-2% vs. the +-1% for Fvco > 3 GHz.
> To be revisited and optimized separately.
>
> Signed-off-by: Alexey Charkov <[email protected]>
> ---
> Changes in v2:
> - Split out the denominator fix into its own patch (thanks Heiko)
> - Reword the commit description for clarity (thanks Quentin and Sebastian)
> - Add relevant clock derivation formulas and key constraints directly into
>   a code comment for easier future reference
> - Link to v1: https://patch.msgid.link/[email protected]

What do you think - is this good for 7.3?

Best regards,
Alexey