RE: [PATCH v3 3/5] clk: samsung: clk-pll: Add support for pll_1061x
"Alim Akhtar" <[email protected]> Wed, 29 Jul 2026 10:42:49 +0530
| Newsgroups | org.kernel.vger.linux-clk,org.infradead.lists.linux-arm-kernel,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.linux-samsung-soc |
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| Message-ID | <[email protected]> |
Hi Alexandru > -----Original Message----- > From: Alexandru Chimac <[email protected]> > Sent: Thursday, July 23, 2026 2:14 AM > To: Krzysztof Kozlowski <[email protected]>; Sylwester Nawrocki > <[email protected]>; Chanwoo Choi <[email protected]>; > Peter Griffin <[email protected]>; Alim Akhtar > <[email protected]>; Michael Turquette > <[email protected]>; Stephen Boyd <[email protected]>; Brian > Masney <[email protected]>; Rob Herring <[email protected]>; Conor > Dooley <[email protected]>; Alexandru Chimac <[email protected]>; > Krzysztof Kozlowski <[email protected]> > Cc: [email protected]; [email protected]; > [email protected]; [email protected]; linux- > [email protected] > Subject: [PATCH v3 3/5] clk: samsung: clk-pll: Add support for pll_1061x > > These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and are similar > to pll_1460x (using CON3 instead of CON1), so the code for that can handle > this PLL with a few small adaptations. > It is good to mention that PLL_1061x is a fractional type PLL and used to supply BLK_MMC and AUD, atleast on 9610 SoC > Signed-off-by: Alexandru Chimac <[email protected]> > --- > drivers/clk/samsung/clk-pll.c | 29 ++++++++++++++++++++++------- > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 23 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index > e74552846ba3..2cda87235fa2 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -781,15 +781,20 @@ static unsigned long > samsung_pll46xx_recalc_rate(struct clk_hw *hw, > u64 fvco = parent_rate; > > pll_con0 = readl_relaxed(pll->con_reg); > - pll_con1 = readl_relaxed(pll->con_reg + 4); > - mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == > pll_1460x) ? > + if (pll->type == pll_1061x) > + pll_con1 = readl_relaxed(pll->con_reg + 0xc); Actually this is PLL_CON3 in UM, not suggesting to use a new variable but a comment here will help. Thanks!