Re: [PATCH 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks

On 7/28/2026 5:32 PM, Konrad Dybcio wrote:
> On 7/24/26 5:00 PM, Luo Jie wrote:
>> Some CMN PLL output clocks require a hardware gate in addition to a
>> fixed rate. The gate control bits reside in the register
>> CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered as a
>> composite clock combining a clk_fixed_rate provider with a clk_gate.
> 
> Would toggling this register in .enable/.disable not be good enough?
> Do we need to register a separate gate?
> 
> Konrad

Yes. Toggling the bit directly in custom .enable/.disable is simpler and
more consistent with the rest of this driver (every other clock here
uses regmap). Will switch to a single clk_hw with hand-written
.enable/.disable/.is_enabled/.recalc_rate ops on
CMN_PLL_OUTPUT_RELATED_1.