Re: [PATCH] clk: qcom: Fix camera rivian PLL configuration settings

On 8/1/2026 1:15 AM, Jagadeesh Kona wrote:
> clk_alpha_pll_write_config() in the PLL configure function skips writes
> to PLL registers when the configured value is 0. However, hardware
> requires USER_CTL_U and CONFIG_CTL_U2 to be explicitly programmed to 0
> for a few rivian PLLs.
> 
> Add a clk_regs_configure() callback to ensure these rivian PLL registers
> are correctly initialized on Glymur, SM8750, and Kaanapali platforms.
> 
> Fixes: 97255eedd690 ("clk: qcom: camcc-glymur: Add camera clock controller driver")
> Fixes: f9580bafd39c ("clk: qcom: camcc: Add camera clock controller driver for SM8750 SoC")
> Fixes: 92aae35f667c ("clk: qcom: camcc: Add support for camera clock controller for Kaanapali")
> Signed-off-by: Jagadeesh Kona <[email protected]>
> ---
>  drivers/clk/qcom/cambistmclkcc-kaanapali.c | 7 +++++++
>  drivers/clk/qcom/cambistmclkcc-sm8750.c    | 7 +++++++
>  drivers/clk/qcom/camcc-glymur.c            | 7 +++++++
>  3 files changed, 21 insertions(+)

Reviewed-by: Taniya Das <[email protected]>

-- 
Thanks,
Taniya Das