Re: [PATCH 0/2] clk: qcom: nord: fix PHY pipe clock halt check and mux ops

On Thu, 16 Jul 2026 16:29:10 +0530, Taniya Das wrote:
> Fix two PHY pipe clock issues in the Nord GCC/NE_GCC drivers: the
> PCIe and USB3 pipe clock branches poll BRANCH_HALT_VOTED, which can
> spuriously time out since the halt bit doesn't toggle reliably while
> the PHY is down. The USB3 pipe clock source muxes use
> clk_regmap_mux_closest_ops, which doesn't park on the reference clock
> when disabled. Switch the branches to BRANCH_HALT_SKIP and convert
> the muxes to clk_regmap_phy_mux_ops, matching existing conventions
> elsewhere in the Qualcomm clock drivers.
> 
> [...]

Applied, thanks!

[1/2] clk: qcom: nord: use BRANCH_HALT_SKIP for PHY pipe clocks
      commit: 3a8a7d597b07ffe388b47fb524827be52c9f7e0f
[2/2] clk: qcom: negcc-nord: use clk_regmap_phy_mux for USB3 pipe clock srcs
      commit: a5c2859ffe9c8e033e2df1ef62357fa5692008f1

Best regards,
-- 
Bjorn Andersson <[email protected]>