Re: [PATCH v5 11/25] clk: mediatek: pll: Factorise pll power on/off sequences
Brian Masney <[email protected]> Mon, 3 Aug 2026 10:39:19 -0400
| Newsgroups | org.kernel.vger.linux-clk,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-mediatek,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.netdev |
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| Message-ID | <[email protected]> |
On Sat, Aug 01, 2026 at 01:20:57PM +0200, Louis-Alexis Eyraud wrote: > In order to prepare the MT8189 SoC support, that requires different > registers to control PLL status and perform reset BAR, and so a > different sets of clock operations, split the pll power on and off > sequences from mtk_pll_prepare/unprepare functions into private > subfunctions. > > Signed-off-by: Louis-Alexis Eyraud <[email protected]> Reviewed-by: Brian Masney <[email protected]>