Re: [PATCH v5 15/25] clk: mediatek: pllfh: Add ops for PLLs using set/clr regs
Brian Masney <[email protected]> Mon, 3 Aug 2026 10:46:21 -0400
| Newsgroups | org.kernel.vger.linux-clk,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-mediatek,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel,org.kernel.vger.netdev |
|---|---|
| Message-ID | <[email protected]> |
On Sat, Aug 01, 2026 at 01:21:01PM +0200, Louis-Alexis Eyraud wrote: > Add new set of PLL FHCTL clock operations, that uses the new prepare > and unprepare methods, added in PLL for MT8189 SoC to support this > logic. > > Signed-off-by: Louis-Alexis Eyraud <[email protected]> Reviewed-by: Brian Masney <[email protected]>