[PATCH 1/2] clk: spacemit: re-enable PLLs after init

The PLL and PLLA init callbacks gate off and reprogram a PLL when its
firmware configuration is absent from the rate table. However, they
leave the PLL gated off after updating the registers.

Re-enable the PLL to complete the sequence and propagate any lock
timeout to clock registration.

Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
Fixes: 3a086236c600 ("clk: spacemit: ccu_pll: add plla type clock")
Signed-off-by: Troy Mitchell <[email protected]>
---
 drivers/clk/spacemit/ccu_pll.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/spacemit/ccu_pll.c b/drivers/clk/spacemit/ccu_pll.c
index d4066a0ed452..f9627da0af37 100644
--- a/drivers/clk/spacemit/ccu_pll.c
+++ b/drivers/clk/spacemit/ccu_pll.c
@@ -148,7 +148,7 @@ static int ccu_pll_init(struct clk_hw *hw)
 	ccu_pll_disable(hw);
 	ccu_pll_update_param(pll, &pll->config.rate_tbl[0]);
 
-	return 0;
+	return ccu_pll_enable(hw);
 }
 
 static const struct ccu_pll_rate_tbl *ccu_plla_lookup_matched_entry(struct ccu_pll *pll)
@@ -252,7 +252,7 @@ static int ccu_plla_init(struct clk_hw *hw)
 	ccu_plla_disable(hw);
 	ccu_plla_update_param(pll, &pll->config.rate_tbl[0]);
 
-	return 0;
+	return ccu_plla_enable(hw);
 }
 
 const struct clk_ops spacemit_ccu_pll_ops = {

-- 
2.55.0