Re: [PATCH] dt-bindings: clock: ti,DM814x-ADPLL: Convert to DT schema

On Tue, Aug 4, 2026 at 3:21=E2=80=AFAM Rob Herring <[email protected]> wrote:
>
> On Sun, Jul 26, 2026 at 12:17:47AM +0530, Bhargav Joshi wrote:
> > Convert the Texas Instruments DM814x ADPLL clock binding to DT schema
> > format. Add 'clock-output-names' as required which was missing in
> > legacy binding, as the driver (clk-adpll.c) mandates it and fails
> > probing if it is missing.
> >
> > Signed-off-by: Bhargav Joshi <[email protected]>
> > ---
> >  .../devicetree/bindings/clock/ti/adpll.txt         |  39 --------
> >  .../bindings/clock/ti/ti,dm814-adpll-clock.yaml    | 108 +++++++++++++=
++++++++
> >  2 files changed, 108 insertions(+), 39 deletions(-)
>
> > diff --git a/Documentation/devicetree/bindings/clock/ti/ti,dm814-adpll-=
clock.yaml b/Documentation/devicetree/bindings/clock/ti/ti,dm814-adpll-cloc=
k.yaml
> > new file mode 100644
> > index 000000000000..7f551dfca030
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/ti/ti,dm814-adpll-clock.y=
aml
> > @@ -0,0 +1,108 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/ti/ti,dm814-adpll-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Texas Instruments DM814x ADPLL Clock
> > +
> > +maintainers:
> > +  - Tony Lindgren <[email protected]>
> > +
> > +description:
> > +  The ADPLL is a register-mapped clock generator found on TI DM814x So=
Cs. It
> > +  provides multiple output clocks from two or three selectable input c=
locks and
> > +  three to four children.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - ti,dm814-adpll-s-clock
> > +      - ti,dm814-adpll-lj-clock
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +  clocks:
> > +    minItems: 2
> > +    maxItems: 3
> > +
> > +  clock-names:
> > +    minItems: 2
> > +    maxItems: 3
> > +
> > +  clock-output-names:
> > +    minItems: 3
> > +    maxItems: 4
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#clock-cells'
> > +  - clocks
> > +  - clock-output-names
> > +
> > +if:
> > +  properties:
> > +    compatible:
> > +      contains:
> > +        const: ti,dm814-adpll-s-clock
> > +then:
> > +  properties:
> > +    clocks:
> > +      minItems: 3
> > +    clock-names:
> > +      items:
> > +        - const: clkinp
> > +        - const: clkinpulow
> > +        - const: clkinphif
>
> This can move to the top level and just 'minItems: 3' here.
yes sure
>
> > +    clock-output-names:
> > +      items:
> > +        - description: dcoclkldo
> > +        - description: clkout
> > +        - description: clkoutx2
> > +        - description: clkouthif
>
> You don't have to document the clock-output-names.
>
Got it. I will drop the item descriptions for clock-output-names.
> > +else:
> > +  properties:
> > +    clocks:
> > +      maxItems: 2
> > +    clock-names:
> > +      items:
> > +        - const: clkinp
> > +        - const: clkinpulow
>
> And just 'maxItems: 2' here.
>
> > +    clock-output-names:
> > +      items:
> > +        - description: dcoclkldo
> > +        - description: clkout
> > +        - description: clkoutldo
>
> And drop. Or maybe just 'maxItems: 3'
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    adpll@40 {
> > +        compatible =3D "ti,dm814-adpll-s-clock";
> > +        reg =3D <0x40 0x40>;
> > +        #clock-cells =3D <1>;
> > +        clocks =3D <&devosc_ck &devosc_ck &devosc_ck>;
> > +        clock-names =3D "clkinp", "clkinpulow", "clkinphif";
> > +        clock-output-names =3D "481c5040.adpll.dcoclkldo",
> > +                             "481c5040.adpll.clkout",
> > +                             "481c5040.adpll.clkoutx2",
> > +                             "481c5040.adpll.clkouthif";
> > +    };
> > +
> > +  - |
> > +    adpll@80 {
> > +        compatible =3D "ti,dm814-adpll-lj-clock";
> > +        reg =3D <0x80 0x30>;
> > +        #clock-cells =3D <1>;
> > +        clocks =3D <&devosc_ck &devosc_ck>;
> > +        clock-names =3D "clkinp", "clkinpulow";
> > +        clock-output-names =3D "481c5080.adpll.dcoclkldo",
> > +                             "481c5080.adpll.clkout",
> > +                             "481c5080.adpll.clkoutldo";
> > +    };
>
> One example is enough.