[PATCH v4 1/2] dt-bindings: clock: qcom: Add LPASS VA CSR HeartBeat pulse clock
Sarath Ganapathiraju via B4 Relay <[email protected]> Wed, 05 Aug 2026 16:03:19 +0530
| Newsgroups | org.kernel.vger.linux-clk,org.kernel.feeds.b4-sent,org.kernel.vger.linux-arm-msm,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
From: Sarath Ganapathiraju <[email protected]> Add a binding for the Qualcomm LPASS VA CSR rate generator node that exposes the lpass_heartbeat_pulse clock on hawi. The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecase and can serve as a periodic wakeup source for the DSP. Signed-off-by: Sarath Ganapathiraju <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> --- .../bindings/clock/qcom,hawi-lpass-va-csr.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml new file mode 100644 index 000000000000..9935173d8bee --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-lpass-va-csr.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,hawi-lpass-va-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS VA CSR heartbeat pulse clock provider + +maintainers: + - Srinivas Kandagatla <[email protected]> + - Sarath Ganapathiraju <[email protected]> + +description: + The LPASS (Low Power Audio Subsystem) VA CSR block contains a rate + generator that produces a periodic HeartBeat Pulse, also known as + the RateGen Pulse. This pulse synchronizes the start of DMAs and + Codec Interfaces for audio usecases and can serve as a periodic + wakeup source for the DSP. + +properties: + compatible: + enum: + - qcom,hawi-lpass-va-csr + + reg: + maxItems: 1 + description: Address and size of the rate generator registers within + the VA CSR block. + + "#clock-cells": + const: 0 + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@7eed000 { + compatible = "qcom,hawi-lpass-va-csr"; + reg = <0x0 0x07eed000 0x0 0x14>; + #clock-cells = <0>; + }; + }; -- 2.34.1