[PATCH v2 0/9] ARM: stm32: add STM32H7R7 and ART-Pi2 support

Add initial mainline support for the STM32H7R7 and the Ruiside ART-Pi2
development board.

The ART-Pi2 boots through first-stage firmware in the STM32 internal flash.
That firmware configures the PLLs and memory interfaces before Linux
executes in place from external XSPI NOR, with 32 MiB of HyperRAM used as
system RAM.  Reprogramming the PLLs from Linux could therefore stop the
instruction stream.

The RCC driver intentionally reconstructs the active clock rates from the
firmware-programmed RCC registers.  It exposes the resulting SYSCLK, bus,
timer, UART and SDMMC clocks, while Linux owns only the peripheral clock
gates used by the initial device tree.  The same RCC probe registers the
reset lines through reset_simple_ops; the first reset consumer is SDMMC1.

The pinctrl driver covers GPIOA-H and GPIOM-P, including the AF0 trace
functions described by the STM32H7RS pin-control data.  The board device
tree enables UART4, TIM5, twelve GPIO banks, two LEDs, the user button and
the four-bit SDMMC1 interface used by the microSD socket.  The socket has
no card detect signal connected to the MCU, so the board uses broken-cd.
ARM noMMU selects DMA_GLOBAL_POOL, so the board reserves a 2 MiB shared DMA
pool for the SDMMC internal DMA descriptor and bounce buffer.

Changes in v2:
- clk: register as a builtin platform driver with a probe instead of
  CLK_OF_DECLARE_DRIVER; switch to devm_of_iomap()/devm_clk_get()/devm
  clock registration; register gates with clk_parent_data; drop the
  unused slab.h include; reverse-Christmas-tree the pll_rate() locals
  and add the missing blank line (all per Brian Masney's review).
- clk: register the RCC reset controller from probe via reset_simple_ops
  (select RESET_SIMPLE), and give the RCC node a single
  "st,stm32h7rs-rcc" compatible so the generic reset-simple platform
  driver no longer competes for the node.
- dts: clock TIM5 from a DT fixed-clock because it is initialized via
  TIMER_OF_DECLARE() before the RCC platform driver.
- dts: use the pinctrl "ranges" offsets for the GPIO bank unit-addresses
  to fix the kernel test robot dtc warnings.
- Add the STM32H7RS files to MAINTAINERS and expand the Kconfig help.

Link to v1:
https://lore.kernel.org/r/MN0PR19MB60912FA1E75E4E55B2E27D34ACCD2@MN0PR19MB6091.namprd19.prod.outlook.com

Tested on an ART-Pi2 with the exact kernel from this series:

- booted an XIP kernel from external NOR to a static-FLAT BusyBox
  userspace;
- detected 32 MiB of HyperRAM;
- used UART4 as early and normal console;
- used TIM5 as clockevent and clocksource;
- RCC bound as a platform driver and registered the reset controller,
  the bus/timer/UART/SDMMC clocks and the peripheral gates;
- registered all twelve GPIO banks, both LEDs and the gpio-key input
  device;
- detected a 59.5 GiB SDXC card through mmci-pl18x, then wrote a 1 MiB
  random file to an ext4 partition, synced, unmounted and remounted it,
  and verified identical SHA-256 hashes before deleting the test file
  and unmounting cleanly;
- built the target DTB with CHECK_DTBS=y and passed dt-doc-validate for
  the changed bindings;
- ran checkpatch on all nine patches with no errors.

The test kernel kept the Cortex-M7 instruction and data caches disabled.
DMA coherency with the data cache enabled remains to be validated
separately.

The only dtbs_check diagnostic is the existing lack of a schema matching
"arm,cortex-m7".

Liu Changjie (9):
  dt-bindings: arm: stm32: add Ruiside ART-Pi2
  dt-bindings: clock: stm32: add STM32H7RS RCC
  clk: stm32: add STM32H7RS RCC driver
  dt-bindings: pinctrl: stm32: add STM32H7RS
  pinctrl: stm32: add STM32H7RS support
  ARM: stm32: add STM32H7R7 platform support
  ARM: dts: stm32: add STM32H7R7 SoC
  ARM: dts: stm32: add Ruiside ART-Pi2 board
  ARM: stm32: document STM32H7R7 support

 Documentation/arch/arm/index.rst              |    1 +
 .../arch/arm/stm32/stm32h7r7-overview.rst     |   28 +
 .../devicetree/bindings/arm/stm32/stm32.yaml  |    3 +
 .../bindings/clock/st,stm32-rcc.yaml          |   73 +-
 .../bindings/pinctrl/st,stm32-pinctrl.yaml    |    7 +-
 .../devicetree/bindings/vendor-prefixes.yaml  |    2 +
 MAINTAINERS                                   |    6 +
 arch/arm/Kconfig.debug                        |   12 +
 arch/arm/boot/dts/st/Makefile                 |    1 +
 arch/arm/boot/dts/st/stm32h7r7.dtsi           |  261 +++
 arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts  |  100 +
 arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi   |   63 +
 arch/arm/include/debug/stm32.S                |    2 +-
 arch/arm/mach-stm32/Kconfig                   |    9 +
 arch/arm/mach-stm32/board-dt.c                |    1 +
 drivers/clk/Kconfig                           |    6 +
 drivers/clk/Makefile                          |    1 +
 drivers/clk/clk-stm32h7rs.c                   |  521 +++++
 drivers/pinctrl/stm32/Kconfig                 |   11 +
 drivers/pinctrl/stm32/Makefile                |    1 +
 drivers/pinctrl/stm32/pinctrl-stm32h7rs.c     | 1849 +++++++++++++++++
 include/dt-bindings/clock/stm32h7rs-clks.h    |   32 +
 include/dt-bindings/mfd/stm32h7rs-rcc.h       |   11 +
 23 files changed, 2985 insertions(+), 16 deletions(-)
 create mode 100644 Documentation/arch/arm/stm32/stm32h7r7-overview.rst
 create mode 100644 arch/arm/boot/dts/st/stm32h7r7.dtsi
 create mode 100644 arch/arm/boot/dts/st/stm32h7r7l8-art-pi2.dts
 create mode 100644 arch/arm/boot/dts/st/stm32h7rs-pinctrl.dtsi
 create mode 100644 drivers/clk/clk-stm32h7rs.c
 create mode 100644 drivers/pinctrl/stm32/pinctrl-stm32h7rs.c
 create mode 100644 include/dt-bindings/clock/stm32h7rs-clks.h
 create mode 100644 include/dt-bindings/mfd/stm32h7rs-rcc.h


base-commit: 248951ddc14de84de3910f9b13f51491a8cd91df
-- 
2.55.0