[PATCH 09/25] dt-bindings: usb: rockchip,dwc3: add RV1106 SoC support

Document the DWC3 USB controller found on the Rockchip RV1106 SoC.

The RV1106 has a USB2-only (high-speed) OTG controller. Unlike the
other supported SoCs it has no dedicated suspend clock: it only needs
the 24 MHz reference clock, the AXI bus clock and the UTMI clock.

Since the top-level clock-names list enforces a fixed order with
"suspend_clk" as the second entry, relax the second and third entries
to enums so that the RV1106 clock set (ref_clk, bus_clk, utmi) can be
expressed, and add a per-SoC clause constraining RV1106 to exactly
these three clocks. The relaxation is required rather than cosmetic:
every other compatible's own clause already agrees with the shared
tuple position-by-position, but RV1106 genuinely reorders it (bus_clk
before utmi, no suspend_clk), and allOf branches are ANDed, so without
loosening the shared entries the two clauses would be unsatisfiable
together.

Signed-off-by: Vladislav Leonov <[email protected]>
---

 .../bindings/usb/rockchip,dwc3.yaml           | 35 ++++++++++++++++---
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
index 0554dbc4b854..86e00f251bdb 100644
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -31,6 +31,7 @@ select:
           - rockchip,rk3568-dwc3
           - rockchip,rk3576-dwc3
           - rockchip,rk3588-dwc3
+          - rockchip,rv1106-dwc3
   required:
     - compatible
 
@@ -44,6 +45,7 @@ properties:
           - rockchip,rk3568-dwc3
           - rockchip,rk3576-dwc3
           - rockchip,rk3588-dwc3
+          - rockchip,rv1106-dwc3
       - const: snps,dwc3
 
   reg:
@@ -58,10 +60,11 @@ properties:
       - description:
           Controller reference clock, must to be 24 MHz
       - description:
-          Controller suspend clock, must to be 24 MHz or 32 KHz
+          Controller suspend clock (must to be 24 MHz or 32 KHz) or
+          Master/Core clock
       - description:
           Master/Core clock, must to be >= 62.5 MHz for SS
-          operation and >= 30MHz for HS operation
+          operation and >= 30MHz for HS operation, or UTMI clock
       - description:
           Controller grf clock OR UTMI clock
       - description:
@@ -71,8 +74,12 @@ properties:
     minItems: 3
     items:
       - const: ref_clk
-      - const: suspend_clk
-      - const: bus_clk
+      - enum:
+          - suspend_clk
+          - bus_clk
+      - enum:
+          - bus_clk
+          - utmi
       - enum:
           - grf_clk
           - utmi
@@ -145,7 +152,10 @@ allOf:
         clocks:
           maxItems: 3
         clock-names:
-          maxItems: 3
+          items:
+            - const: ref_clk
+            - const: suspend_clk
+            - const: bus_clk
   - if:
       properties:
         compatible:
@@ -161,6 +171,21 @@ allOf:
             - const: bus_clk
             - const: utmi
             - const: pipe
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: rockchip,rv1106-dwc3
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: ref_clk
+            - const: bus_clk
+            - const: utmi
 
 examples:
   - |
-- 
2.47.3