[PATCH 12/25] ARM: dts: rockchip: Add I2C nodes for RV1106
Vladislav Leonov <[email protected]>
| Newsgroups | org.kernel.vger.linux-clk,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-rockchip,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
|---|---|
| Message-ID | <[email protected]> |
Rockchip RV1106 has five I2C controllers. Add the i2c0-i2c4 nodes together with their aliases, using the m0 pinmux by default. All nodes default to status = "disabled" and are enabled per-board. Signed-off-by: Vladislav Leonov <[email protected]> --- arch/arm/boot/dts/rockchip/rv1106.dtsi | 70 ++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi index 43db3b1dd4b8..43d992e3e2d6 100644 --- a/arch/arm/boot/dts/rockchip/rv1106.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi @@ -25,6 +25,11 @@ aliases { gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; }; cpus { @@ -155,6 +160,32 @@ gic: interrupt-controller@ff1f0000 { #address-cells = <0>; }; + i2c0: i2c@ff310000 { + compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg = <0xff310000 0x1000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@ff320000 { + compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg = <0xff320000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + status = "disabled"; + }; + gpio0_ioc: syscon@ff388000 { compatible = "rockchip,rv1106-gpio0-ioc", "syscon"; reg = <0xff388000 0x8000>; @@ -204,6 +235,45 @@ u2phy_otg: otg-port { }; }; + i2c2: i2c@ff450000 { + compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg = <0xff450000 0x1000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff460000 { + compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg = <0xff460000 0x1000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + status = "disabled"; + }; + + i2c4: i2c@ff470000 { + compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c"; + reg = <0xff470000 0x1000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + status = "disabled"; + }; + uart0: serial@ff4a0000 { compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart"; reg = <0xff4a0000 0x100>; -- 2.47.3